[llvm] r343570 - [AArch64][v8.5A] Add MTE system instructions
Oliver Stannard via llvm-commits
llvm-commits at lists.llvm.org
Tue Oct 2 02:48:43 PDT 2018
Author: olista01
Date: Tue Oct 2 02:48:43 2018
New Revision: 343570
URL: http://llvm.org/viewvc/llvm-project?rev=343570&view=rev
Log:
[AArch64][v8.5A] Add MTE system instructions
The Memory Tagging Extension adds system instructions for data cache
maintenance, implemented as new operands to the DC instruction.
Patch by Pablo Barrio!
Differential revision: https://reviews.llvm.org/D52487
Added:
llvm/trunk/test/MC/AArch64/armv8.5a-mte.s
llvm/trunk/test/MC/Disassembler/AArch64/armv8.5a-mte.txt
Modified:
llvm/trunk/lib/Target/AArch64/AArch64SystemOperands.td
llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
Modified: llvm/trunk/lib/Target/AArch64/AArch64SystemOperands.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64SystemOperands.td?rev=343570&r1=343569&r2=343570&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64SystemOperands.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64SystemOperands.td Tue Oct 2 02:48:43 2018
@@ -108,6 +108,27 @@ def : DC<"CVAP", 0b011, 0b0111, 0b1100,
let Requires = [{ {AArch64::FeatureCacheDeepPersist} }] in
def : DC<"CVADP", 0b011, 0b0111, 0b1101, 0b001>;
+let Requires = [{ {AArch64::FeatureMTE} }] in {
+def : DC<"IGVAC", 0b000, 0b0111, 0b0110, 0b011>;
+def : DC<"IGSW", 0b000, 0b0111, 0b0110, 0b100>;
+def : DC<"CGSW", 0b000, 0b0111, 0b1010, 0b100>;
+def : DC<"CIGSW", 0b000, 0b0111, 0b1110, 0b100>;
+def : DC<"CGVAC", 0b011, 0b0111, 0b1010, 0b011>;
+def : DC<"CGVAP", 0b011, 0b0111, 0b1100, 0b011>;
+def : DC<"CGVADP", 0b011, 0b0111, 0b1101, 0b011>;
+def : DC<"CIGVAC", 0b011, 0b0111, 0b1110, 0b011>;
+def : DC<"GVA", 0b011, 0b0111, 0b0100, 0b011>;
+def : DC<"IGDVAC", 0b000, 0b0111, 0b0110, 0b101>;
+def : DC<"IGDSW", 0b000, 0b0111, 0b0110, 0b110>;
+def : DC<"CGDSW", 0b000, 0b0111, 0b1010, 0b110>;
+def : DC<"CIGDSW", 0b000, 0b0111, 0b1110, 0b110>;
+def : DC<"CGDVAC", 0b011, 0b0111, 0b1010, 0b101>;
+def : DC<"CGDVAP", 0b011, 0b0111, 0b1100, 0b101>;
+def : DC<"CGDVADP", 0b011, 0b0111, 0b1101, 0b101>;
+def : DC<"CIGDVAC", 0b011, 0b0111, 0b1110, 0b101>;
+def : DC<"GZVA", 0b011, 0b0111, 0b0100, 0b100>;
+}
+
//===----------------------------------------------------------------------===//
// IC (instruction cache maintenance) instruction options.
//===----------------------------------------------------------------------===//
Modified: llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp?rev=343570&r1=343569&r2=343570&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp Tue Oct 2 02:48:43 2018
@@ -2825,6 +2825,7 @@ static const struct Extension {
{ "lse", {AArch64::FeatureLSE} },
{ "predctrl", {AArch64::FeaturePredCtrl} },
{ "ccdp", {AArch64::FeatureCacheDeepPersist} },
+ { "mte", {AArch64::FeatureMTE} },
// FIXME: Unsupported extensions
{ "pan", {} },
Added: llvm/trunk/test/MC/AArch64/armv8.5a-mte.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/armv8.5a-mte.s?rev=343570&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/armv8.5a-mte.s (added)
+++ llvm/trunk/test/MC/AArch64/armv8.5a-mte.s Tue Oct 2 02:48:43 2018
@@ -0,0 +1,60 @@
+// RUN: llvm-mc -triple aarch64 -show-encoding -mattr=+mte < %s | FileCheck %s
+// RUN: not llvm-mc -triple aarch64 -show-encoding -mattr=+v8.5a < %s 2>&1 | FileCheck %s --check-prefix=NOMTE
+// RUN: not llvm-mc -triple aarch64 -show-encoding -mattr=-mte < %s 2>&1 | FileCheck %s --check-prefix=NOMTE
+
+dc igvac, x0
+dc igsw, x1
+dc cgsw, x2
+dc cigsw, x3
+dc cgvac, x4
+dc cgvap, x5
+dc cgvadp, x6
+dc cigvac, x7
+dc gva, x8
+dc igdvac, x9
+dc igdsw, x10
+dc cgdsw, x11
+dc cigdsw, x12
+dc cgdvac, x13
+dc cgdvap, x14
+dc cgdvadp, x15
+dc cigdvac, x16
+dc gzva, x17
+
+// CHECK: dc igvac, x0 // encoding: [0x60,0x76,0x08,0xd5]
+// CHECK: dc igsw, x1 // encoding: [0x81,0x76,0x08,0xd5]
+// CHECK: dc cgsw, x2 // encoding: [0x82,0x7a,0x08,0xd5]
+// CHECK: dc cigsw, x3 // encoding: [0x83,0x7e,0x08,0xd5]
+// CHECK: dc cgvac, x4 // encoding: [0x64,0x7a,0x0b,0xd5]
+// CHECK: dc cgvap, x5 // encoding: [0x65,0x7c,0x0b,0xd5]
+// CHECK: dc cgvadp, x6 // encoding: [0x66,0x7d,0x0b,0xd5]
+// CHECK: dc cigvac, x7 // encoding: [0x67,0x7e,0x0b,0xd5]
+// CHECK: dc gva, x8 // encoding: [0x68,0x74,0x0b,0xd5]
+// CHECK: dc igdvac, x9 // encoding: [0xa9,0x76,0x08,0xd5]
+// CHECK: dc igdsw, x10 // encoding: [0xca,0x76,0x08,0xd5]
+// CHECK: dc cgdsw, x11 // encoding: [0xcb,0x7a,0x08,0xd5]
+// CHECK: dc cigdsw, x12 // encoding: [0xcc,0x7e,0x08,0xd5]
+// CHECK: dc cgdvac, x13 // encoding: [0xad,0x7a,0x0b,0xd5]
+// CHECK: dc cgdvap, x14 // encoding: [0xae,0x7c,0x0b,0xd5]
+// CHECK: dc cgdvadp, x15 // encoding: [0xaf,0x7d,0x0b,0xd5]
+// CHECK: dc cigdvac, x16 // encoding: [0xb0,0x7e,0x0b,0xd5]
+// CHECK: dc gzva, x17 // encoding: [0x91,0x74,0x0b,0xd5]
+
+// NOMTE: DC IGVAC requires mte
+// NOMTE: DC IGSW requires mte
+// NOMTE: DC CGSW requires mte
+// NOMTE: DC CIGSW requires mte
+// NOMTE: DC CGVAC requires mte
+// NOMTE: DC CGVAP requires mte
+// NOMTE: DC CGVADP requires mte
+// NOMTE: DC CIGVAC requires mte
+// NOMTE: DC GVA requires mte
+// NOMTE: DC IGDVAC requires mte
+// NOMTE: DC IGDSW requires mte
+// NOMTE: DC CGDSW requires mte
+// NOMTE: DC CIGDSW requires mte
+// NOMTE: DC CGDVAC requires mte
+// NOMTE: DC CGDVAP requires mte
+// NOMTE: DC CGDVADP requires mte
+// NOMTE: DC CIGDVAC requires mte
+// NOMTE: DC GZVA requires mte
Added: llvm/trunk/test/MC/Disassembler/AArch64/armv8.5a-mte.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/AArch64/armv8.5a-mte.txt?rev=343570&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/AArch64/armv8.5a-mte.txt (added)
+++ llvm/trunk/test/MC/Disassembler/AArch64/armv8.5a-mte.txt Tue Oct 2 02:48:43 2018
@@ -0,0 +1,60 @@
+# RUN: llvm-mc -triple=aarch64 -mattr=+mte -disassemble < %s | FileCheck %s
+# RUN: llvm-mc -triple=aarch64 -mattr=+v8.5a -disassemble < %s | FileCheck %s --check-prefix=NOMTE
+# RUN: llvm-mc -triple=aarch64 -mattr=-mte -disassemble < %s | FileCheck %s --check-prefix=NOMTE
+
+[0x60,0x76,0x08,0xd5]
+[0x81,0x76,0x08,0xd5]
+[0x82,0x7a,0x08,0xd5]
+[0x83,0x7e,0x08,0xd5]
+[0x64,0x7a,0x0b,0xd5]
+[0x65,0x7c,0x0b,0xd5]
+[0x66,0x7d,0x0b,0xd5]
+[0x67,0x7e,0x0b,0xd5]
+[0x68,0x74,0x0b,0xd5]
+[0xa9,0x76,0x08,0xd5]
+[0xca,0x76,0x08,0xd5]
+[0xcb,0x7a,0x08,0xd5]
+[0xcc,0x7e,0x08,0xd5]
+[0xad,0x7a,0x0b,0xd5]
+[0xae,0x7c,0x0b,0xd5]
+[0xaf,0x7d,0x0b,0xd5]
+[0xb0,0x7e,0x0b,0xd5]
+[0x91,0x74,0x0b,0xd5]
+
+# CHECK: dc igvac, x0
+# CHECK: dc igsw, x1
+# CHECK: dc cgsw, x2
+# CHECK: dc cigsw, x3
+# CHECK: dc cgvac, x4
+# CHECK: dc cgvap, x5
+# CHECK: dc cgvadp, x6
+# CHECK: dc cigvac, x7
+# CHECK: dc gva, x8
+# CHECK: dc igdvac, x9
+# CHECK: dc igdsw, x10
+# CHECK: dc cgdsw, x11
+# CHECK: dc cigdsw, x12
+# CHECK: dc cgdvac, x13
+# CHECK: dc cgdvap, x14
+# CHECK: dc cgdvadp, x15
+# CHECK: dc cigdvac, x16
+# CHECK: dc gzva, x17
+
+# NOMTE: sys #0, c7, c6, #3, x0
+# NOMTE: sys #0, c7, c6, #4, x1
+# NOMTE: sys #0, c7, c10, #4, x2
+# NOMTE: sys #0, c7, c14, #4, x3
+# NOMTE: sys #3, c7, c10, #3, x4
+# NOMTE: sys #3, c7, c12, #3, x5
+# NOMTE: sys #3, c7, c13, #3, x6
+# NOMTE: sys #3, c7, c14, #3, x7
+# NOMTE: sys #3, c7, c4, #3, x8
+# NOMTE: sys #0, c7, c6, #5, x9
+# NOMTE: sys #0, c7, c6, #6, x10
+# NOMTE: sys #0, c7, c10, #6, x11
+# NOMTE: sys #0, c7, c14, #6, x12
+# NOMTE: sys #3, c7, c10, #5, x13
+# NOMTE: sys #3, c7, c12, #5, x14
+# NOMTE: sys #3, c7, c13, #5, x15
+# NOMTE: sys #3, c7, c14, #5, x16
+# NOMTE: sys #3, c7, c4, #4, x17
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