[PATCH] D52486: [AArch64][v8.5A] Add MTE as an optional AArch64 extension

[Oliver Stannard via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL343563: [AArch64][v8.5A] Add MTE as an optional AArch64 extension (authored by olista01, committed by ).
Herald added a subscriber: kristina.

Changed prior to commit:
  https://reviews.llvm.org/D52486?vs=166903&id=167897#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D52486

Files:
  llvm/trunk/include/llvm/Support/AArch64TargetParser.def
  llvm/trunk/include/llvm/Support/TargetParser.h
  llvm/trunk/lib/Target/AArch64/AArch64.td
  llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h
  llvm/trunk/unittests/Support/TargetParserTest.cpp


Index: llvm/trunk/lib/Target/AArch64/AArch64.td
===================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64.td
+++ llvm/trunk/lib/Target/AArch64/AArch64.td
@@ -233,6 +233,9 @@
 def FeatureRandGen : SubtargetFeature<"rand", "HasRandGen",
     "true", "Enable Random Number generation instructions" >;
 
+def FeatureMTE : SubtargetFeature<"mte", "HasMTE",
+    "true", "Enable Memory Tagging Extension" >;
+
 //===----------------------------------------------------------------------===//
 // Architectures.
 //
Index: llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h
===================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h
+++ llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h
@@ -103,6 +103,7 @@
   bool HasCCDP = false;
   bool HasBTI = false;
   bool HasRandGen = false;
+  bool HasMTE = false;
 
   // HasZeroCycleRegMove - Has zero-cycle register mov instructions.
   bool HasZeroCycleRegMove = false;
@@ -328,6 +329,7 @@
   bool hasCCDP() { return HasCCDP; }
   bool hasBTI() { return HasBTI; }
   bool hasRandGen() { return HasRandGen; }
+  bool hasMTE() { return HasMTE; }
 
   bool isLittleEndian() const { return IsLittle; }
 
Index: llvm/trunk/unittests/Support/TargetParserTest.cpp
===================================================================
--- llvm/trunk/unittests/Support/TargetParserTest.cpp
+++ llvm/trunk/unittests/Support/TargetParserTest.cpp
@@ -966,7 +966,8 @@
                               {"sve", "nosve", "+sve", "-sve"},
                               {"dotprod", "nodotprod", "+dotprod", "-dotprod"},
                               {"rcpc", "norcpc", "+rcpc", "-rcpc" },
-                              {"rng", "norng", "+rand", "-rand"}};
+                              {"rng", "norng", "+rand", "-rand"},
+                              {"memtag", "nomemtag", "+mte", "-mte"}};
 
   for (unsigned i = 0; i < array_lengthof(ArchExt); i++) {
     EXPECT_EQ(StringRef(ArchExt[i][2]),
Index: llvm/trunk/include/llvm/Support/TargetParser.h
===================================================================
--- llvm/trunk/include/llvm/Support/TargetParser.h
+++ llvm/trunk/include/llvm/Support/TargetParser.h
@@ -181,6 +181,7 @@
   AEK_AES =         1 << 16,
   AEK_FP16FML =     1 << 17,
   AEK_RAND =        1 << 18,
+  AEK_MTE =         1 << 19,
 };
 
 StringRef getCanonicalArchName(StringRef Arch);
Index: llvm/trunk/include/llvm/Support/AArch64TargetParser.def
===================================================================
--- llvm/trunk/include/llvm/Support/AArch64TargetParser.def
+++ llvm/trunk/include/llvm/Support/AArch64TargetParser.def
@@ -71,6 +71,7 @@
 AARCH64_ARCH_EXT_NAME("sve",      AArch64::AEK_SVE,      "+sve",  "-sve")
 AARCH64_ARCH_EXT_NAME("rcpc",     AArch64::AEK_RCPC,     "+rcpc", "-rcpc")
 AARCH64_ARCH_EXT_NAME("rng",      AArch64::AEK_RAND,     "+rand",  "-rand")
+AARCH64_ARCH_EXT_NAME("memtag",   AArch64::AEK_MTE,      "+mte",   "-mte")
 #undef AARCH64_ARCH_EXT_NAME
 
 #ifndef AARCH64_CPU_NAME


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