[PATCH] D52736: [AMDGPU] Fixed SIInstrInfo::getOpSize to handle subregs

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


================
Comment at: llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.h:735-736
+    if (MO.isReg()) {
+      if (unsigned SubReg = MO.getSubReg())
+        return RI.getSubRegIndexLaneMask(SubReg).getNumLanes() * 4;
+    }
----------------
rampitec wrote:
> arsenm wrote:
> > I think this silently will break if we start using 16-bit subregs. Can you assert that this number is consistent with the size of the super-reg?
> In fact a lot will break if we start using 16 bit subregs. I would like to add the assert, but that is exactly the problem, one cannot know subreg's size without assuming target specific subreg layout. I.e. I do not see how to do it w/o listing all possible subregs in our target. Also note that MRI.getMaxLaneMaskForVReg() will happily return -1 for the whole register. Any ideas?
You can just assert against the size of the subreg class? Something like (getRegSizeInBits(getSubClassWithSubReg(getRegClass(Reg)) >= 32)?


Repository:
  rL LLVM

https://reviews.llvm.org/D52736