[PATCH] D52757: [X86] Bring back the MOV64r0 pseudo instruction

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
craig.topper added reviewers: RKSimon, spatel, t.p.northover, MatzeB.
Herald added a subscriber: qcolombet.

This patch brings back the MOV64r0 pseudo instruction for zeroing a 64-bit register. This replaces the SUBREG_TO_REG MOV32r0 sequence we use today. Post register allocation we will rewrite the MOV64r0 to a 32-bit xor with an implicit def of the 64-bit register similar to what we do for the various XMM/YMM/ZMM zeroing pseudos.

My main motivation is to enable the spill optimization in foldMemoryOperandImpl. As we were seeing some code that repeatedly did "xor eax, eax; store eax;" to spill several registers with a new xor for each store. With this optimization enabled we get a store of a 0 immediate instead of an xor. Though I admit the ideal solution would be one xor where there are multiple spills. I don't believe we have a test case that shows this optimization in here. I'll see if I can try to reduce one from the code were looking at.

There's definitely some other machine CSE(and maybe other passes) behavior changes exposed by this patch. So it seems like there might be some other deficiencies in SUBREG_TO_REG handling.


https://reviews.llvm.org/D52757

Files:
  lib/Target/X86/X86FastISel.cpp
  lib/Target/X86/X86ISelDAGToDAG.cpp
  lib/Target/X86/X86InstrCompiler.td
  lib/Target/X86/X86InstrInfo.cpp
  lib/Target/X86/X86SpeculativeLoadHardening.cpp
  test/CodeGen/X86/GlobalISel/constant.ll
  test/CodeGen/X86/avg.ll
  test/CodeGen/X86/hoist-spill.ll
  test/CodeGen/X86/machine-cse.ll
  test/CodeGen/X86/madd.ll
  test/CodeGen/X86/mmx-arith.ll
  test/CodeGen/X86/swifterror.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D52757.167853.patch
Type: text/x-patch
Size: 56507 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20181002/f15bd240/attachment-0001.bin>