[llvm] r343521 - [globalisel] Add a combiner helpers for extending loads and use them in a pre-legalize combiner for AArch64
Daniel Sanders via llvm-commits
llvm-commits at lists.llvm.org
Mon Oct 1 11:56:47 PDT 2018
Author: dsanders
Date: Mon Oct 1 11:56:47 2018
New Revision: 343521
URL: http://llvm.org/viewvc/llvm-project?rev=343521&view=rev
Log:
[globalisel] Add a combiner helpers for extending loads and use them in a pre-legalize combiner for AArch64
Summary: Depends on D45541
Reviewers: ab, aditya_nandakumar, bogner, rtereshin, volkan, rovka, javed.absar, aemerson
Subscribers: aemerson, rengolin, mgorny, javed.absar, kristof.beyls, llvm-commits
Differential Revision: https://reviews.llvm.org/D45543
Added:
llvm/trunk/lib/Target/AArch64/AArch64PreLegalizerCombiner.cpp
llvm/trunk/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-extending-loads.mir
Modified:
llvm/trunk/include/llvm/CodeGen/GlobalISel/Combiner.h
llvm/trunk/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
llvm/trunk/include/llvm/CodeGen/GlobalISel/CombinerInfo.h
llvm/trunk/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
llvm/trunk/lib/CodeGen/GlobalISel/Combiner.cpp
llvm/trunk/lib/CodeGen/GlobalISel/CombinerHelper.cpp
llvm/trunk/lib/Target/AArch64/AArch64.h
llvm/trunk/lib/Target/AArch64/AArch64TargetMachine.cpp
llvm/trunk/lib/Target/AArch64/CMakeLists.txt
llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll
llvm/trunk/test/CodeGen/AArch64/GlobalISel/gisel-commandline-option.ll
llvm/trunk/test/CodeGen/AArch64/O0-pipeline.ll
Modified: llvm/trunk/include/llvm/CodeGen/GlobalISel/Combiner.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/GlobalISel/Combiner.h?rev=343521&r1=343520&r2=343521&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/GlobalISel/Combiner.h (original)
+++ llvm/trunk/include/llvm/CodeGen/GlobalISel/Combiner.h Mon Oct 1 11:56:47 2018
@@ -24,6 +24,16 @@ class CombinerInfo;
class TargetPassConfig;
class MachineFunction;
+class CombinerChangeObserver {
+public:
+ virtual ~CombinerChangeObserver() {}
+
+ /// An instruction was erased.
+ virtual void erasedInstr(MachineInstr &MI) = 0;
+ /// An instruction was created and inseerted into the function.
+ virtual void createdInstr(MachineInstr &MI) = 0;
+};
+
class Combiner {
public:
Combiner(CombinerInfo &CombinerInfo, const TargetPassConfig *TPC);
Modified: llvm/trunk/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/GlobalISel/CombinerHelper.h?rev=343521&r1=343520&r2=343521&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/GlobalISel/CombinerHelper.h (original)
+++ llvm/trunk/include/llvm/CodeGen/GlobalISel/CombinerHelper.h Mon Oct 1 11:56:47 2018
@@ -20,6 +20,7 @@
namespace llvm {
+class CombinerChangeObserver;
class MachineIRBuilder;
class MachineRegisterInfo;
class MachineInstr;
@@ -27,14 +28,22 @@ class MachineInstr;
class CombinerHelper {
MachineIRBuilder &Builder;
MachineRegisterInfo &MRI;
+ CombinerChangeObserver &Observer;
+
+ void eraseInstr(MachineInstr &MI);
+ void scheduleForVisit(MachineInstr &MI);
public:
- CombinerHelper(MachineIRBuilder &B);
+ CombinerHelper(CombinerChangeObserver &Observer, MachineIRBuilder &B);
/// If \p MI is COPY, try to combine it.
/// Returns true if MI changed.
bool tryCombineCopy(MachineInstr &MI);
+ /// If \p MI is extend that consumes the result of a load, try to combine it.
+ /// Returns true if MI changed.
+ bool tryCombineExtendingLoads(MachineInstr &MI);
+
/// Try to transform \p MI by using all of the above
/// combine functions. Returns true if changed.
bool tryCombine(MachineInstr &MI);
Modified: llvm/trunk/include/llvm/CodeGen/GlobalISel/CombinerInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/GlobalISel/CombinerInfo.h?rev=343521&r1=343520&r2=343521&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/GlobalISel/CombinerInfo.h (original)
+++ llvm/trunk/include/llvm/CodeGen/GlobalISel/CombinerInfo.h Mon Oct 1 11:56:47 2018
@@ -17,10 +17,12 @@
#include <cassert>
namespace llvm {
+class CombinerChangeObserver;
class LegalizerInfo;
class MachineInstr;
class MachineIRBuilder;
class MachineRegisterInfo;
+
// Contains information relevant to enabling/disabling various combines for a
// pass.
class CombinerInfo {
@@ -41,7 +43,8 @@ public:
/// illegal ops that are created.
bool LegalizeIllegalOps; // TODO: Make use of this.
const LegalizerInfo *LInfo;
- virtual bool combine(MachineInstr &MI, MachineIRBuilder &B) const = 0;
+ virtual bool combine(CombinerChangeObserver &Observer, MachineInstr &MI,
+ MachineIRBuilder &B) const = 0;
};
} // namespace llvm
Modified: llvm/trunk/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h?rev=343521&r1=343520&r2=343521&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h (original)
+++ llvm/trunk/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h Mon Oct 1 11:56:47 2018
@@ -60,11 +60,6 @@ struct MachineIRBuilderState {
class MachineIRBuilderBase {
MachineIRBuilderState State;
- const TargetInstrInfo &getTII() {
- assert(State.TII && "TargetInstrInfo is not set");
- return *State.TII;
- }
-
void validateTruncExt(unsigned Dst, unsigned Src, bool IsExtend);
protected:
@@ -107,6 +102,11 @@ public:
MachineIRBuilderBase(const MachineIRBuilderState &BState) : State(BState) {}
+ const TargetInstrInfo &getTII() {
+ assert(State.TII && "TargetInstrInfo is not set");
+ return *State.TII;
+ }
+
/// Getter for the function we currently build.
MachineFunction &getMF() {
assert(State.MF && "MachineFunction is not set");
Modified: llvm/trunk/lib/CodeGen/GlobalISel/Combiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GlobalISel/Combiner.cpp?rev=343521&r1=343520&r2=343521&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/GlobalISel/Combiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/GlobalISel/Combiner.cpp Mon Oct 1 11:56:47 2018
@@ -25,6 +25,34 @@
using namespace llvm;
+namespace {
+/// This class acts as the glue the joins the CombinerHelper to the overall
+/// Combine algorithm. The CombinerHelper is intended to report the
+/// modifications it makes to the MIR to the CombinerChangeObserver and the
+/// observer subclass will act on these events. In this case, instruction
+/// erasure will cancel any future visits to the erased instruction and
+/// instruction creation will schedule that instruction for a future visit.
+/// Other Combiner implementations may require more complex behaviour from
+/// their CombinerChangeObserver subclass.
+class WorkListMaintainer : public CombinerChangeObserver {
+ using WorkListTy = GISelWorkList<512>;
+ WorkListTy &WorkList;
+
+public:
+ WorkListMaintainer(WorkListTy &WorkList) : WorkList(WorkList) {}
+ virtual ~WorkListMaintainer() {}
+
+ void erasedInstr(MachineInstr &MI) override {
+ LLVM_DEBUG(dbgs() << "Erased: "; MI.print(dbgs()); dbgs() << "\n");
+ WorkList.remove(&MI);
+ }
+ void createdInstr(MachineInstr &MI) override {
+ LLVM_DEBUG(dbgs() << "Created: "; MI.print(dbgs()); dbgs() << "\n");
+ WorkList.insert(&MI);
+ }
+};
+}
+
Combiner::Combiner(CombinerInfo &Info, const TargetPassConfig *TPC)
: CInfo(Info), TPC(TPC) {
(void)this->TPC; // FIXME: Remove when used.
@@ -53,6 +81,7 @@ bool Combiner::combineMachineInstrs(Mach
// down RPOT.
Changed = false;
GISelWorkList<512> WorkList;
+ WorkListMaintainer Observer(WorkList);
for (MachineBasicBlock *MBB : post_order(&MF)) {
if (MBB->empty())
continue;
@@ -72,7 +101,7 @@ bool Combiner::combineMachineInstrs(Mach
while (!WorkList.empty()) {
MachineInstr *CurrInst = WorkList.pop_back_val();
LLVM_DEBUG(dbgs() << "Try combining " << *CurrInst << "\n";);
- Changed |= CInfo.combine(*CurrInst, Builder);
+ Changed |= CInfo.combine(Observer, *CurrInst, Builder);
}
MFChanged |= Changed;
} while (Changed);
Modified: llvm/trunk/lib/CodeGen/GlobalISel/CombinerHelper.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GlobalISel/CombinerHelper.cpp?rev=343521&r1=343520&r2=343521&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/GlobalISel/CombinerHelper.cpp (original)
+++ llvm/trunk/lib/CodeGen/GlobalISel/CombinerHelper.cpp Mon Oct 1 11:56:47 2018
@@ -6,18 +6,28 @@
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
+#include "llvm/CodeGen/GlobalISel/Combiner.h"
#include "llvm/CodeGen/GlobalISel/CombinerHelper.h"
#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
#include "llvm/CodeGen/GlobalISel/Utils.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/TargetInstrInfo.h"
#define DEBUG_TYPE "gi-combine"
using namespace llvm;
-CombinerHelper::CombinerHelper(MachineIRBuilder &B) :
- Builder(B), MRI(Builder.getMF().getRegInfo()) {}
+CombinerHelper::CombinerHelper(CombinerChangeObserver &Observer,
+ MachineIRBuilder &B)
+ : Builder(B), MRI(Builder.getMF().getRegInfo()), Observer(Observer) {}
+
+void CombinerHelper::eraseInstr(MachineInstr &MI) {
+ Observer.erasedInstr(MI);
+}
+void CombinerHelper::scheduleForVisit(MachineInstr &MI) {
+ Observer.createdInstr(MI);
+}
bool CombinerHelper::tryCombineCopy(MachineInstr &MI) {
if (MI.getOpcode() != TargetOpcode::COPY)
@@ -36,6 +46,208 @@ bool CombinerHelper::tryCombineCopy(Mach
return false;
}
+namespace {
+struct PreferredTuple {
+ LLT Ty; // The result type of the extend.
+ unsigned ExtendOpcode; // G_ANYEXT/G_SEXT/G_ZEXT
+ MachineInstr *MI;
+};
+
+/// Select a preference between two uses. CurrentUse is the current preference
+/// while *ForCandidate is attributes of the candidate under consideration.
+PreferredTuple ChoosePreferredUse(PreferredTuple &CurrentUse,
+ const LLT &TyForCandidate,
+ unsigned OpcodeForCandidate,
+ MachineInstr *MIForCandidate) {
+ if (!CurrentUse.Ty.isValid()) {
+ if (CurrentUse.ExtendOpcode == OpcodeForCandidate)
+ return {TyForCandidate, OpcodeForCandidate, MIForCandidate};
+ if (CurrentUse.ExtendOpcode == TargetOpcode::G_ANYEXT &&
+ (OpcodeForCandidate == TargetOpcode::G_SEXT ||
+ OpcodeForCandidate == TargetOpcode::G_ZEXT ||
+ OpcodeForCandidate == TargetOpcode::G_ANYEXT))
+ return {TyForCandidate, OpcodeForCandidate, MIForCandidate};
+ return CurrentUse;
+ }
+
+ // We permit the extend to hoist through basic blocks but this is only
+ // sensible if the target has extending loads. If you end up lowering back
+ // into a load and extend during the legalizer then the end result is
+ // hoisting the extend up to the load.
+
+ // Prefer defined extensions to undefined extensions as these are more
+ // likely to reduce the number of instructions.
+ if (OpcodeForCandidate == TargetOpcode::G_ANYEXT &&
+ CurrentUse.ExtendOpcode != TargetOpcode::G_ANYEXT)
+ return CurrentUse;
+ else if (CurrentUse.ExtendOpcode == TargetOpcode::G_ANYEXT &&
+ OpcodeForCandidate != TargetOpcode::G_ANYEXT)
+ return {TyForCandidate, OpcodeForCandidate, MIForCandidate};
+
+ // Prefer sign extensions to zero extensions as sign-extensions tend to be
+ // more expensive.
+ if (CurrentUse.Ty == TyForCandidate) {
+ if (CurrentUse.ExtendOpcode == TargetOpcode::G_SEXT &&
+ OpcodeForCandidate == TargetOpcode::G_ZEXT)
+ return CurrentUse;
+ else if (CurrentUse.ExtendOpcode == TargetOpcode::G_ZEXT &&
+ OpcodeForCandidate == TargetOpcode::G_SEXT)
+ return {TyForCandidate, OpcodeForCandidate, MIForCandidate};
+ }
+
+ // This is potentially target specific. We've chosen the largest type
+ // because G_TRUNC is usually free. One potential catch with this is that
+ // some targets have a reduced number of larger registers than smaller
+ // registers and this choice potentially increases the live-range for the
+ // larger value.
+ if (TyForCandidate.getSizeInBits() > CurrentUse.Ty.getSizeInBits()) {
+ return {TyForCandidate, OpcodeForCandidate, MIForCandidate};
+ }
+ return CurrentUse;
+};
+} // end anonymous namespace
+
+bool CombinerHelper::tryCombineExtendingLoads(MachineInstr &MI) {
+ // We match the loads and follow the uses to the extend instead of matching
+ // the extends and following the def to the load. This is because the load
+ // must remain in the same position for correctness (unless we also add code
+ // to find a safe place to sink it) whereas the extend is freely movable.
+ // It also prevents us from duplicating the load for the volatile case or just
+ // for performance.
+
+ if (MI.getOpcode() != TargetOpcode::G_LOAD &&
+ MI.getOpcode() != TargetOpcode::G_SEXTLOAD &&
+ MI.getOpcode() != TargetOpcode::G_ZEXTLOAD)
+ return false;
+
+ auto &LoadValue = MI.getOperand(0);
+ assert(LoadValue.isReg() && "Result wasn't a register?");
+
+ LLT LoadValueTy = MRI.getType(LoadValue.getReg());
+ if (!LoadValueTy.isScalar())
+ return false;
+
+ // Find the preferred type aside from the any-extends (unless it's the only
+ // one) and non-extending ops. We'll emit an extending load to that type and
+ // and emit a variant of (extend (trunc X)) for the others according to the
+ // relative type sizes. At the same time, pick an extend to use based on the
+ // extend involved in the chosen type.
+ PreferredTuple Preferred = {LLT(),
+ MI.getOpcode() == TargetOpcode::G_LOAD
+ ? TargetOpcode::G_ANYEXT
+ : MI.getOpcode() == TargetOpcode::G_SEXTLOAD
+ ? TargetOpcode::G_SEXT
+ : TargetOpcode::G_ZEXT,
+ nullptr};
+ for (auto &UseMI : MRI.use_instructions(LoadValue.getReg())) {
+ if (UseMI.getOpcode() == TargetOpcode::G_SEXT ||
+ UseMI.getOpcode() == TargetOpcode::G_ZEXT || !Preferred.Ty.isValid())
+ Preferred = ChoosePreferredUse(Preferred,
+ MRI.getType(UseMI.getOperand(0).getReg()),
+ UseMI.getOpcode(), &UseMI);
+ }
+
+ // There were no extends
+ if (!Preferred.MI)
+ return false;
+ // It should be impossible to chose an extend without selecting a different
+ // type since by definition the result of an extend is larger.
+ assert(Preferred.Ty != LoadValueTy && "Extending to same type?");
+
+ // Rewrite the load and schedule the canonical use for erasure.
+ const auto TruncateUse = [](MachineIRBuilder &Builder, MachineOperand &UseMO,
+ unsigned DstReg, unsigned SrcReg) {
+ MachineInstr &UseMI = *UseMO.getParent();
+ MachineBasicBlock &UseMBB = *UseMI.getParent();
+
+ Builder.setInsertPt(UseMBB, MachineBasicBlock::iterator(UseMI));
+ Builder.buildTrunc(DstReg, SrcReg);
+ };
+
+ // Rewrite the load to the chosen extending load.
+ unsigned ChosenDstReg = Preferred.MI->getOperand(0).getReg();
+ MI.setDesc(
+ Builder.getTII().get(Preferred.ExtendOpcode == TargetOpcode::G_SEXT
+ ? TargetOpcode::G_SEXTLOAD
+ : Preferred.ExtendOpcode == TargetOpcode::G_ZEXT
+ ? TargetOpcode::G_ZEXTLOAD
+ : TargetOpcode::G_LOAD));
+
+ // Rewrite all the uses to fix up the types.
+ SmallVector<MachineInstr *, 1> ScheduleForErase;
+ for (auto &UseMO : MRI.use_operands(LoadValue.getReg())) {
+ MachineInstr *UseMI = UseMO.getParent();
+
+ // If the extend is compatible with the preferred extend then we should fix
+ // up the type and extend so that it uses the preferred use.
+ if (UseMI->getOpcode() == Preferred.ExtendOpcode ||
+ UseMI->getOpcode() == TargetOpcode::G_ANYEXT) {
+ unsigned UseDstReg = UseMI->getOperand(0).getReg();
+ unsigned UseSrcReg = UseMI->getOperand(1).getReg();
+ const LLT &UseDstTy = MRI.getType(UseDstReg);
+ if (UseDstReg != ChosenDstReg) {
+ if (Preferred.Ty == UseDstTy) {
+ // If the use has the same type as the preferred use, then merge
+ // the vregs and erase the extend. For example:
+ // %1:_(s8) = G_LOAD ...
+ // %2:_(s32) = G_SEXT %1(s8)
+ // %3:_(s32) = G_ANYEXT %1(s8)
+ // ... = ... %3(s32)
+ // rewrites to:
+ // %2:_(s32) = G_SEXTLOAD ...
+ // ... = ... %2(s32)
+ MRI.replaceRegWith(UseDstReg, ChosenDstReg);
+ ScheduleForErase.push_back(UseMO.getParent());
+ Observer.erasedInstr(*UseMO.getParent());
+ } else if (Preferred.Ty.getSizeInBits() < UseDstTy.getSizeInBits()) {
+ // If the preferred size is smaller, then keep the extend but extend
+ // from the result of the extending load. For example:
+ // %1:_(s8) = G_LOAD ...
+ // %2:_(s32) = G_SEXT %1(s8)
+ // %3:_(s64) = G_ANYEXT %1(s8)
+ // ... = ... %3(s64)
+ /// rewrites to:
+ // %2:_(s32) = G_SEXTLOAD ...
+ // %3:_(s64) = G_ANYEXT %2:_(s32)
+ // ... = ... %3(s64)
+ MRI.replaceRegWith(UseSrcReg, ChosenDstReg);
+ } else {
+ // If the preferred size is large, then insert a truncate. For
+ // example:
+ // %1:_(s8) = G_LOAD ...
+ // %2:_(s64) = G_SEXT %1(s8)
+ // %3:_(s32) = G_ZEXT %1(s8)
+ // ... = ... %3(s32)
+ /// rewrites to:
+ // %2:_(s64) = G_SEXTLOAD ...
+ // %4:_(s8) = G_TRUNC %2:_(s32)
+ // %3:_(s64) = G_ZEXT %2:_(s8)
+ // ... = ... %3(s64)
+ TruncateUse(Builder, UseMO, MI.getOperand(0).getReg(), ChosenDstReg);
+ }
+ continue;
+ }
+ // The use is (one of) the uses of the preferred use we chose earlier.
+ // We're going to update the load to def this value later so just erase
+ // the old extend.
+ ScheduleForErase.push_back(UseMO.getParent());
+ Observer.erasedInstr(*UseMO.getParent());
+ continue;
+ }
+
+ // The use isn't an extend. Truncate back to the type we originally loaded.
+ // This is free on many targets.
+ TruncateUse(Builder, UseMO, MI.getOperand(0).getReg(), ChosenDstReg);
+ }
+ for (auto &EraseMI : ScheduleForErase)
+ EraseMI->eraseFromParent();
+ MI.getOperand(0).setReg(ChosenDstReg);
+
+ return true;
+}
+
bool CombinerHelper::tryCombine(MachineInstr &MI) {
- return tryCombineCopy(MI);
+ if (tryCombineCopy(MI))
+ return true;
+ return tryCombineExtendingLoads(MI);
}
Modified: llvm/trunk/lib/Target/AArch64/AArch64.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64.h?rev=343521&r1=343520&r2=343521&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64.h (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64.h Mon Oct 1 11:56:47 2018
@@ -53,6 +53,7 @@ FunctionPass *createAArch64CollectLOHPas
InstructionSelector *
createAArch64InstructionSelector(const AArch64TargetMachine &,
AArch64Subtarget &, AArch64RegisterBankInfo &);
+FunctionPass *createAArch64PreLegalizeCombiner();
void initializeAArch64A53Fix835769Pass(PassRegistry&);
void initializeAArch64A57FPLoadBalancingPass(PassRegistry&);
@@ -65,6 +66,7 @@ void initializeAArch64DeadRegisterDefini
void initializeAArch64ExpandPseudoPass(PassRegistry&);
void initializeAArch64LoadStoreOptPass(PassRegistry&);
void initializeAArch64SIMDInstrOptPass(PassRegistry&);
+void initializeAArch64PreLegalizerCombinerPass(PassRegistry&);
void initializeAArch64PromoteConstantPass(PassRegistry&);
void initializeAArch64RedundantCopyEliminationPass(PassRegistry&);
void initializeAArch64StorePairSuppressPass(PassRegistry&);
Added: llvm/trunk/lib/Target/AArch64/AArch64PreLegalizerCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64PreLegalizerCombiner.cpp?rev=343521&view=auto
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64PreLegalizerCombiner.cpp (added)
+++ llvm/trunk/lib/Target/AArch64/AArch64PreLegalizerCombiner.cpp Mon Oct 1 11:56:47 2018
@@ -0,0 +1,108 @@
+//=== lib/CodeGen/GlobalISel/AArch64PreLegalizerCombiner.cpp --------------===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This pass does combining of machine instructions at the generic MI level,
+// before the legalizer.
+//
+//===----------------------------------------------------------------------===//
+
+#include "AArch64TargetMachine.h"
+#include "llvm/CodeGen/GlobalISel/Combiner.h"
+#include "llvm/CodeGen/GlobalISel/CombinerHelper.h"
+#include "llvm/CodeGen/GlobalISel/CombinerInfo.h"
+#include "llvm/CodeGen/GlobalISel/MIPatternMatch.h"
+#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/TargetPassConfig.h"
+#include "llvm/Support/Debug.h"
+
+#define DEBUG_TYPE "aarch64-prelegalizer-combiner"
+
+using namespace llvm;
+using namespace MIPatternMatch;
+
+namespace {
+class AArch64PreLegalizerCombinerInfo : public CombinerInfo {
+public:
+ AArch64PreLegalizerCombinerInfo()
+ : CombinerInfo(/*AllowIllegalOps*/ true, /*ShouldLegalizeIllegal*/ false,
+ /*LegalizerInfo*/ nullptr) {}
+ virtual bool combine(CombinerChangeObserver &Observer, MachineInstr &MI,
+ MachineIRBuilder &B) const override;
+};
+
+bool AArch64PreLegalizerCombinerInfo::combine(CombinerChangeObserver &Observer,
+ MachineInstr &MI,
+ MachineIRBuilder &B) const {
+ CombinerHelper Helper(Observer, B);
+
+ switch (MI.getOpcode()) {
+ default:
+ return false;
+ case TargetOpcode::G_LOAD:
+ case TargetOpcode::G_SEXTLOAD:
+ case TargetOpcode::G_ZEXTLOAD:
+ return Helper.tryCombineExtendingLoads(MI);
+ }
+
+ return false;
+}
+
+// Pass boilerplate
+// ================
+
+class AArch64PreLegalizerCombiner : public MachineFunctionPass {
+public:
+ static char ID;
+
+ AArch64PreLegalizerCombiner();
+
+ StringRef getPassName() const override { return "AArch64PreLegalizerCombiner"; }
+
+ bool runOnMachineFunction(MachineFunction &MF) override;
+
+ void getAnalysisUsage(AnalysisUsage &AU) const override;
+};
+}
+
+void AArch64PreLegalizerCombiner::getAnalysisUsage(AnalysisUsage &AU) const {
+ AU.addRequired<TargetPassConfig>();
+ AU.setPreservesCFG();
+ getSelectionDAGFallbackAnalysisUsage(AU);
+ MachineFunctionPass::getAnalysisUsage(AU);
+}
+
+AArch64PreLegalizerCombiner::AArch64PreLegalizerCombiner() : MachineFunctionPass(ID) {
+ initializeAArch64PreLegalizerCombinerPass(*PassRegistry::getPassRegistry());
+}
+
+bool AArch64PreLegalizerCombiner::runOnMachineFunction(MachineFunction &MF) {
+ if (MF.getProperties().hasProperty(
+ MachineFunctionProperties::Property::FailedISel))
+ return false;
+ auto *TPC = &getAnalysis<TargetPassConfig>();
+ AArch64PreLegalizerCombinerInfo PCInfo;
+ Combiner C(PCInfo, TPC);
+ return C.combineMachineInstrs(MF);
+}
+
+char AArch64PreLegalizerCombiner::ID = 0;
+INITIALIZE_PASS_BEGIN(AArch64PreLegalizerCombiner, DEBUG_TYPE,
+ "Combine AArch64 machine instrs before legalization",
+ false, false)
+INITIALIZE_PASS_DEPENDENCY(TargetPassConfig)
+INITIALIZE_PASS_END(AArch64PreLegalizerCombiner, DEBUG_TYPE,
+ "Combine AArch64 machine instrs before legalization", false,
+ false)
+
+
+namespace llvm {
+FunctionPass *createAArch64PreLegalizeCombiner() {
+ return new AArch64PreLegalizerCombiner();
+}
+} // end namespace llvm
Modified: llvm/trunk/lib/Target/AArch64/AArch64TargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64TargetMachine.cpp?rev=343521&r1=343520&r2=343521&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64TargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64TargetMachine.cpp Mon Oct 1 11:56:47 2018
@@ -158,6 +158,7 @@ extern "C" void LLVMInitializeAArch64Tar
initializeAArch64ExpandPseudoPass(*PR);
initializeAArch64LoadStoreOptPass(*PR);
initializeAArch64SIMDInstrOptPass(*PR);
+ initializeAArch64PreLegalizerCombinerPass(*PR);
initializeAArch64PromoteConstantPass(*PR);
initializeAArch64RedundantCopyEliminationPass(*PR);
initializeAArch64StorePairSuppressPass(*PR);
@@ -348,6 +349,7 @@ public:
bool addPreISel() override;
bool addInstSelector() override;
bool addIRTranslator() override;
+ void addPreLegalizeMachineIR() override;
bool addLegalizeMachineIR() override;
bool addRegBankSelect() override;
void addPreGlobalInstructionSelect() override;
@@ -449,6 +451,10 @@ bool AArch64PassConfig::addIRTranslator(
return false;
}
+void AArch64PassConfig::addPreLegalizeMachineIR() {
+ addPass(createAArch64PreLegalizeCombiner());
+}
+
bool AArch64PassConfig::addLegalizeMachineIR() {
addPass(new Legalizer());
return false;
Modified: llvm/trunk/lib/Target/AArch64/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/CMakeLists.txt?rev=343521&r1=343520&r2=343521&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/CMakeLists.txt (original)
+++ llvm/trunk/lib/Target/AArch64/CMakeLists.txt Mon Oct 1 11:56:47 2018
@@ -43,6 +43,7 @@ add_llvm_target(AArch64CodeGen
AArch64LoadStoreOptimizer.cpp
AArch64MacroFusion.cpp
AArch64MCInstLower.cpp
+ AArch64PreLegalizerCombiner.cpp
AArch64PromoteConstant.cpp
AArch64PBQPRegAlloc.cpp
AArch64RegisterBankInfo.cpp
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll?rev=343521&r1=343520&r2=343521&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll Mon Oct 1 11:56:47 2018
@@ -54,7 +54,7 @@ false:
}
-; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to legalize instruction: %0:_(s24) = G_LOAD %1:_(p0) :: (load 3 from `i24* undef`, align 1) (in function: odd_type_load)
+; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to legalize instruction: %2:_(s32) = G_ZEXTLOAD %1:_(p0) :: (load 3 from `i24* undef`, align 1) (in function: odd_type_load)
; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for odd_type_load
; FALLBACK-WITH-REPORT-OUT-LABEL: odd_type_load
define i32 @odd_type_load() {
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/gisel-commandline-option.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/gisel-commandline-option.ll?rev=343521&r1=343520&r2=343521&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/gisel-commandline-option.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/gisel-commandline-option.ll Mon Oct 1 11:56:47 2018
@@ -36,6 +36,7 @@
; RUN: -debug-pass=Structure %s -o /dev/null 2>&1 | FileCheck %s --check-prefix DISABLED
; ENABLED: IRTranslator
+; ENABLED-NEXT: PreLegalizerCombiner
; ENABLED-NEXT: Legalizer
; ENABLED-NEXT: RegBankSelect
; ENABLED-O0-NEXT: Localizer
Added: llvm/trunk/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-extending-loads.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-extending-loads.mir?rev=343521&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-extending-loads.mir (added)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-extending-loads.mir Mon Oct 1 11:56:47 2018
@@ -0,0 +1,450 @@
+# RUN: llc -O0 -run-pass=aarch64-prelegalizer-combiner -global-isel %s -o - | FileCheck %s
+
+--- |
+ target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
+ target triple = "aarch64--"
+ define void @test_anyext(i8* %addr) {
+ entry:
+ ret void
+ }
+ define void @test_anyext_with_copy(i8* %addr) {
+ entry:
+ ret void
+ }
+ define void @test_signext(i8* %addr) {
+ entry:
+ ret void
+ }
+ define void @test_zeroext(i8* %addr) {
+ entry:
+ ret void
+ }
+ define void @test_2anyext(i8* %addr) {
+ entry:
+ ret void
+ }
+ define void @test_1anyext_1signext(i8* %addr) {
+ entry:
+ ret void
+ }
+ define void @test_1xor_1signext(i8* %addr) {
+ entry:
+ ret void
+ }
+ define void @test_1anyext_1zeroext(i8* %addr) {
+ entry:
+ ret void
+ }
+ define void @test_1signext_1zeroext(i8* %addr) {
+ entry:
+ ret void
+ }
+ define void @test_1anyext64_1signext32(i8* %addr) {
+ entry:
+ ret void
+ }
+ define void @test_1anyext32_1signext64(i8* %addr) {
+ entry:
+ ret void
+ }
+ define void @test_2anyext32_1signext64(i8* %addr) {
+ entry:
+ ret void
+ }
+ define void @test_multiblock_anyext(i8* %addr) {
+ entry:
+ ret void
+ }
+ define void @test_multiblock_signext(i8* %addr) {
+ entry:
+ ret void
+ }
+ define void @test_multiblock_zeroext(i8* %addr) {
+ entry:
+ ret void
+ }
+ define void @test_multiblock_2anyext(i8* %addr) {
+ entry:
+ ret void
+ }
+ define void @test_multiblock_1anyext64_1signext32(i8* %addr) {
+ entry:
+ ret void
+ }
+ define void @test_multiblock_1anyext32_1signext64(i8* %addr) {
+ entry:
+ ret void
+ }
+ define void @test_multiblock_2anyext32_1signext64(i8* %addr) {
+ entry:
+ ret void
+ }
+...
+
+---
+name: test_anyext
+body: |
+ bb.0.entry:
+ liveins: $x0
+ ; CHECK-LABEL: name: test_anyext
+ ; CHECK: [[T0:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK: [[T1:%[0-9]+]]:_(s32) = G_LOAD [[T0]](p0) :: (load 1 from %ir.addr)
+ ; CHECK: $w0 = COPY [[T1]](s32)
+ %0:_(p0) = COPY $x0
+ %1:_(s8) = G_LOAD %0 :: (load 1 from %ir.addr)
+ %2:_(s32) = G_ANYEXT %1
+ $w0 = COPY %2
+...
+
+---
+name: test_anyext_with_copy
+body: |
+ bb.0.entry:
+ liveins: $x0
+ ; CHECK-LABEL: name: test_anyext
+ ; CHECK: [[T0:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK: [[T1:%[0-9]+]]:_(s32) = G_LOAD [[T0]](p0) :: (load 1 from %ir.addr)
+ ; CHECK: $w0 = COPY [[T1]](s32)
+ %0:_(p0) = COPY $x0
+ %1:_(s8) = G_LOAD %0 :: (load 1 from %ir.addr)
+ %2:_(s8) = COPY %1
+ %3:_(s32) = G_ANYEXT %1
+ $w0 = COPY %3
+...
+
+---
+name: test_signext
+body: |
+ bb.0.entry:
+ liveins: $x0
+ ; CHECK-LABEL: name: test_signext
+ ; CHECK: [[T0:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK: [[T1:%[0-9]+]]:_(s32) = G_SEXTLOAD [[T0]](p0) :: (load 1 from %ir.addr)
+ ; CHECK: $w0 = COPY [[T1]](s32)
+ %0:_(p0) = COPY $x0
+ %1:_(s8) = G_LOAD %0 :: (load 1 from %ir.addr)
+ %2:_(s32) = G_SEXT %1
+ $w0 = COPY %2
+...
+
+---
+name: test_zeroext
+body: |
+ bb.0.entry:
+ liveins: $x0
+ ; CHECK-LABEL: name: test_zeroext
+ ; CHECK: [[T0:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK: [[T1:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[T0]](p0) :: (load 1 from %ir.addr)
+ ; CHECK: $w0 = COPY [[T1]](s32)
+ %0:_(p0) = COPY $x0
+ %1:_(s8) = G_LOAD %0 :: (load 1 from %ir.addr)
+ %2:_(s32) = G_ZEXT %1
+ $w0 = COPY %2
+...
+
+---
+name: test_2anyext
+body: |
+ bb.0.entry:
+ liveins: $x0
+ ; CHECK-LABEL: name: test_2anyext
+ ; CHECK: [[T0:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK: [[T1:%[0-9]+]]:_(s32) = G_LOAD [[T0]](p0) :: (load 1 from %ir.addr)
+ ; CHECK: $w0 = COPY [[T1]](s32)
+ ; CHECK: $w1 = COPY [[T1]](s32)
+ %0:_(p0) = COPY $x0
+ %1:_(s8) = G_LOAD %0 :: (load 1 from %ir.addr)
+ %2:_(s32) = G_ANYEXT %1
+ %3:_(s32) = G_ANYEXT %1
+ $w0 = COPY %2
+ $w1 = COPY %3
+...
+
+---
+name: test_1anyext_1signext
+body: |
+ bb.0.entry:
+ liveins: $x0
+ ; CHECK-LABEL: name: test_1anyext_1signext
+ ; CHECK: [[T0:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK: [[T1:%[0-9]+]]:_(s32) = G_SEXTLOAD [[T0]](p0) :: (load 1 from %ir.addr)
+ ; CHECK: $w0 = COPY [[T1]](s32)
+ ; CHECK: $w1 = COPY [[T1]](s32)
+ %0:_(p0) = COPY $x0
+ %1:_(s8) = G_LOAD %0 :: (load 1 from %ir.addr)
+ %2:_(s32) = G_ANYEXT %1
+ %3:_(s32) = G_SEXT %1
+ $w0 = COPY %2
+ $w1 = COPY %3
+...
+
+---
+name: test_1xor_1signext
+body: |
+ bb.0.entry:
+ liveins: $x0
+ ; CHECK-LABEL: name: test_1xor_1signext
+ ; CHECK: [[T0:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK: [[T1:%[0-9]+]]:_(s32) = G_SEXTLOAD [[T0]](p0) :: (load 1 from %ir.addr)
+ ; CHECK: [[T2:%[0-9]+]]:_(s8) = G_TRUNC [[T1]]
+ ; CHECK: [[T3:%[0-9]+]]:_(s8) = G_XOR [[T2]], {{%[0-9]+}}
+ ; CHECK: [[T4:%[0-9]+]]:_(s32) = G_ANYEXT [[T3]]
+ ; CHECK: $w0 = COPY [[T4]](s32)
+ ; CHECK: $w1 = COPY [[T1]](s32)
+ %0:_(p0) = COPY $x0
+ %1:_(s8) = G_LOAD %0 :: (load 1 from %ir.addr)
+ %2:_(s8) = G_CONSTANT i32 -1
+ %3:_(s8) = G_XOR %1, %2
+ %5:_(s32) = G_ANYEXT %3
+ %6:_(s32) = G_SEXT %1
+ $w0 = COPY %5
+ $w1 = COPY %6
+...
+
+---
+name: test_1anyext_1zeroext
+body: |
+ bb.0.entry:
+ liveins: $x0
+ ; CHECK-LABEL: name: test_1anyext_1zeroext
+ ; CHECK: [[T0:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK: [[T1:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[T0]](p0) :: (load 1 from %ir.addr)
+ ; CHECK: $w0 = COPY [[T1]](s32)
+ ; CHECK: $w1 = COPY [[T1]](s32)
+ %0:_(p0) = COPY $x0
+ %1:_(s8) = G_LOAD %0 :: (load 1 from %ir.addr)
+ %2:_(s32) = G_ANYEXT %1
+ %3:_(s32) = G_ZEXT %1
+ $w0 = COPY %2
+ $w1 = COPY %3
+...
+
+---
+name: test_1signext_1zeroext
+body: |
+ bb.0.entry:
+ liveins: $x0
+ ; CHECK-LABEL: name: test_1signext_1zeroext
+ ; CHECK: [[T0:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK: [[T1:%[0-9]+]]:_(s32) = G_SEXTLOAD [[T0]](p0) :: (load 1 from %ir.addr)
+ ; CHECK: [[T2:%[0-9]+]]:_(s8) = G_TRUNC [[T1]]
+ ; CHECK: [[T3:%[0-9]+]]:_(s32) = G_ZEXT [[T2]]
+ ; CHECK: $w0 = COPY [[T3]](s32)
+ ; CHECK: $w1 = COPY [[T1]](s32)
+ %0:_(p0) = COPY $x0
+ %1:_(s8) = G_LOAD %0 :: (load 1 from %ir.addr)
+ %2:_(s32) = G_ZEXT %1
+ %3:_(s32) = G_SEXT %1
+ $w0 = COPY %2
+ $w1 = COPY %3
+...
+
+---
+name: test_1anyext64_1signext32
+body: |
+ bb.0.entry:
+ liveins: $x0
+ ; CHECK-LABEL: name: test_1anyext64_1signext32
+ ; CHECK: [[T0:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK: [[T1:%[0-9]+]]:_(s32) = G_SEXTLOAD [[T0]](p0) :: (load 1 from %ir.addr)
+ ; CHECK: [[T2:%[0-9]+]]:_(s64) = G_ANYEXT [[T1]]
+ ; CHECK: $x0 = COPY [[T2]](s64)
+ ; CHECK: $w1 = COPY [[T1]](s32)
+ %0:_(p0) = COPY $x0
+ %1:_(s8) = G_LOAD %0 :: (load 1 from %ir.addr)
+ %2:_(s64) = G_ANYEXT %1
+ %3:_(s32) = G_SEXT %1
+ $x0 = COPY %2
+ $w1 = COPY %3
+...
+
+---
+name: test_1anyext32_1signext64
+body: |
+ bb.0.entry:
+ liveins: $x0
+ ; CHECK-LABEL: name: test_1anyext32_1signext64
+ ; CHECK: [[T0:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK: [[T1:%[0-9]+]]:_(s64) = G_SEXTLOAD [[T0]](p0) :: (load 1 from %ir.addr)
+ ; CHECK: [[T2:%[0-9]+]]:_(s8) = G_TRUNC [[T1]]
+ ; CHECK: [[T3:%[0-9]+]]:_(s32) = G_ANYEXT [[T2]]
+ ; CHECK: $w0 = COPY [[T3]](s32)
+ ; CHECK: $x1 = COPY [[T1]](s64)
+ %0:_(p0) = COPY $x0
+ %1:_(s8) = G_LOAD %0 :: (load 1 from %ir.addr)
+ %2:_(s32) = G_ANYEXT %1
+ %3:_(s64) = G_SEXT %1
+ $w0 = COPY %2
+ $x1 = COPY %3
+...
+
+---
+name: test_2anyext32_1signext64
+body: |
+ bb.0.entry:
+ liveins: $x0
+ ; CHECK-LABEL: name: test_2anyext32_1signext64
+ ; CHECK: [[T0:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK: [[T1:%[0-9]+]]:_(s64) = G_SEXTLOAD [[T0]](p0) :: (load 1 from %ir.addr)
+ ; CHECK: [[T2:%[0-9]+]]:_(s8) = G_TRUNC [[T1]]
+ ; CHECK: [[T3:%[0-9]+]]:_(s32) = G_ANYEXT [[T2]]
+ ; CHECK: [[T4:%[0-9]+]]:_(s8) = G_TRUNC [[T1]]
+ ; CHECK: [[T5:%[0-9]+]]:_(s32) = G_ANYEXT [[T4]]
+ ; CHECK: $w0 = COPY [[T3]](s32)
+ ; CHECK: $x1 = COPY [[T1]](s64)
+ ; CHECK: $w2 = COPY [[T5]](s32)
+ %0:_(p0) = COPY $x0
+ %1:_(s8) = G_LOAD %0 :: (load 1 from %ir.addr)
+ %2:_(s32) = G_ANYEXT %1
+ %3:_(s64) = G_SEXT %1
+ %4:_(s32) = G_ANYEXT %1
+ $w0 = COPY %2
+ $x1 = COPY %3
+ $w2 = COPY %4
+...
+
+---
+name: test_multiblock_anyext
+body: |
+ bb.0.entry:
+ liveins: $x0
+ ; CHECK-LABEL: name: test_multiblock_anyext
+ ; CHECK: [[T0:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK: [[T1:%[0-9]+]]:_(s32) = G_LOAD [[T0]](p0) :: (load 1 from %ir.addr)
+ ; CHECK: G_BR %bb.1
+ ; CHECK: $w0 = COPY [[T1]](s32)
+ %0:_(p0) = COPY $x0
+ %1:_(s8) = G_LOAD %0 :: (load 1 from %ir.addr)
+ G_BR %bb.1
+ bb.1:
+ %2:_(s32) = G_ANYEXT %1
+ $w0 = COPY %2
+...
+
+---
+name: test_multiblock_signext
+body: |
+ bb.0.entry:
+ liveins: $x0
+ ; CHECK-LABEL: name: test_multiblock_signext
+ ; CHECK: [[T0:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK: [[T1:%[0-9]+]]:_(s32) = G_SEXTLOAD [[T0]](p0) :: (load 1 from %ir.addr)
+ ; CHECK: $w0 = COPY [[T1]](s32)
+ %0:_(p0) = COPY $x0
+ %1:_(s8) = G_LOAD %0 :: (load 1 from %ir.addr)
+ G_BR %bb.1
+ bb.1:
+ %2:_(s32) = G_SEXT %1
+ $w0 = COPY %2
+...
+
+---
+name: test_multiblock_zeroext
+body: |
+ bb.0.entry:
+ liveins: $x0
+ ; CHECK-LABEL: name: test_multiblock_zeroext
+ ; CHECK: [[T0:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK: [[T1:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[T0]](p0) :: (load 1 from %ir.addr)
+ ; CHECK: $w0 = COPY [[T1]](s32)
+ %0:_(p0) = COPY $x0
+ %1:_(s8) = G_LOAD %0 :: (load 1 from %ir.addr)
+ G_BR %bb.1
+ bb.1:
+ %2:_(s32) = G_ZEXT %1
+ $w0 = COPY %2
+...
+
+---
+name: test_multiblock_2anyext
+body: |
+ bb.0.entry:
+ liveins: $x0
+ ; CHECK-LABEL: name: test_multiblock
+ ; CHECK: [[T0:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK: [[T1:%[0-9]+]]:_(s32) = G_LOAD [[T0]](p0) :: (load 1 from %ir.addr)
+ ; CHECK: $w0 = COPY [[T1]](s32)
+ ; CHECK: $w1 = COPY [[T1]](s32)
+ %0:_(p0) = COPY $x0
+ %1:_(s8) = G_LOAD %0 :: (load 1 from %ir.addr)
+ %2:_(s32) = G_ANYEXT %1
+ G_BR %bb.1
+ bb.1:
+ %3:_(s32) = G_ANYEXT %1
+ $w0 = COPY %2
+ $w1 = COPY %3
+...
+
+---
+name: test_multiblock_1anyext64_1signext32
+body: |
+ bb.0.entry:
+ liveins: $x0
+ ; CHECK-LABEL: name: test_multiblock_1anyext64_1signext32
+ ; CHECK: [[T0:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK: [[T1:%[0-9]+]]:_(s32) = G_SEXTLOAD [[T0]](p0) :: (load 1 from %ir.addr)
+ ; CHECK: G_BR %bb.1
+ ; CHECK: [[T2:%[0-9]+]]:_(s64) = G_ANYEXT [[T1]]
+ ; CHECK: $x0 = COPY [[T2]](s64)
+ ; CHECK: $w1 = COPY [[T1]](s32)
+ %0:_(p0) = COPY $x0
+ %1:_(s8) = G_LOAD %0 :: (load 1 from %ir.addr)
+ G_BR %bb.1
+ bb.1:
+ %2:_(s64) = G_ANYEXT %1
+ %3:_(s32) = G_SEXT %1
+ $x0 = COPY %2
+ $w1 = COPY %3
+...
+
+---
+name: test_multiblock_1anyext32_1signext64
+body: |
+ bb.0.entry:
+ liveins: $x0
+ ; CHECK-LABEL: name: test_multiblock_1anyext32_1signext64
+ ; CHECK: [[T0:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK: [[T1:%[0-9]+]]:_(s64) = G_SEXTLOAD [[T0]](p0) :: (load 1 from %ir.addr)
+ ; CHECK: G_BR %bb.1
+ ; CHECK: [[T2:%[0-9]+]]:_(s8) = G_TRUNC [[T1]]
+ ; CHECK: [[T3:%[0-9]+]]:_(s32) = G_ANYEXT [[T2]]
+ ; CHECK: $w0 = COPY [[T3]](s32)
+ ; CHECK: $x1 = COPY [[T1]](s64)
+ %0:_(p0) = COPY $x0
+ %1:_(s8) = G_LOAD %0 :: (load 1 from %ir.addr)
+ G_BR %bb.1
+ bb.1:
+ %2:_(s32) = G_ANYEXT %1
+ %3:_(s64) = G_SEXT %1
+ $w0 = COPY %2
+ $x1 = COPY %3
+...
+
+---
+name: test_multiblock_2anyext32_1signext64
+body: |
+ bb.0.entry:
+ liveins: $x0
+ ; CHECK-LABEL: name: test_multiblock_2anyext32_1signext64
+ ; CHECK: [[T0:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK: [[T1:%[0-9]+]]:_(s64) = G_SEXTLOAD [[T0]](p0) :: (load 1 from %ir.addr)
+ ; CHECK: [[T2:%[0-9]+]]:_(s8) = G_TRUNC [[T1]]
+ ; CHECK: [[T3:%[0-9]+]]:_(s32) = G_ANYEXT [[T2]]
+ ; CHECK: G_BR %bb.1
+ ; CHECK: [[T4:%[0-9]+]]:_(s8) = G_TRUNC [[T1]]
+ ; CHECK: [[T5:%[0-9]+]]:_(s32) = G_ANYEXT [[T4]]
+ ; CHECK: $w0 = COPY [[T5]](s32)
+ ; CHECK: $x1 = COPY [[T1]](s64)
+ ; CHECK: $w2 = COPY [[T3]](s32)
+ %0:_(p0) = COPY $x0
+ %1:_(s8) = G_LOAD %0 :: (load 1 from %ir.addr)
+ %4:_(s32) = G_ANYEXT %1
+ G_BR %bb.1
+ bb.1:
+ %2:_(s32) = G_ANYEXT %1
+ %3:_(s64) = G_SEXT %1
+ $w0 = COPY %2
+ $x1 = COPY %3
+ $w2 = COPY %4
+...
+
Modified: llvm/trunk/test/CodeGen/AArch64/O0-pipeline.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/O0-pipeline.ll?rev=343521&r1=343520&r2=343521&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/O0-pipeline.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/O0-pipeline.ll Mon Oct 1 11:56:47 2018
@@ -33,6 +33,7 @@
; CHECK-NEXT: Insert stack protectors
; CHECK-NEXT: Module Verifier
; CHECK-NEXT: IRTranslator
+; CHECK-NEXT: AArch64PreLegalizerCombiner
; CHECK-NEXT: Legalizer
; CHECK-NEXT: RegBankSelect
; CHECK-NEXT: Localizer
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