[PATCH] D52740: [X86] ALU/ADC RMW instructions should use the WriteRMW sequence class

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon created this revision.
RKSimon added reviewers: craig.topper, zvi, pcordes, courbet.
Herald added a subscriber: gbedwell.
Herald added a reviewer: andreadb.

I was expecting this to be a nfc but Silvermont seems to be setup a little differently:

// A folded store needs a cycle on MEC_RSV for the store data, but it does not
// need an extra port cycle to recompute the address.
def : WriteRes<WriteRMW, [SLM_MEC_RSV]>;

So moving from WriteStore to WriteRMW reduces predicted port pressure. From what I can tell this is correct but I wanted to confirm with some Intel guys as my knowledge of SLM is very weak.


Repository:
  rL LLVM

https://reviews.llvm.org/D52740

Files:
  lib/Target/X86/X86Schedule.td
  test/tools/llvm-mca/X86/SLM/resources-x86_64.s

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