[llvm] r343499 - [X86] Enable load folding in the test shrinking code
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Mon Oct 1 10:10:50 PDT 2018
Author: ctopper
Date: Mon Oct 1 10:10:50 2018
New Revision: 343499
URL: http://llvm.org/viewvc/llvm-project?rev=343499&view=rev
Log:
[X86] Enable load folding in the test shrinking code
This patch adds load folding support to the test shrinking code. This was noticed missing in the review for D52669
Differential Revision: https://reviews.llvm.org/D52699
Modified:
llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
llvm/trunk/test/CodeGen/X86/test-shrink.ll
Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp?rev=343499&r1=343498&r2=343499&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Mon Oct 1 10:10:50 2018
@@ -3412,7 +3412,7 @@ void X86DAGToDAGISel::Select(SDNode *Nod
MVT VT;
int SubRegOp;
- unsigned Op;
+ unsigned ROpc, MOpc;
// For each of these checks we need to be careful if the sign flag is
// being used. It is only safe to use the sign flag in two conditions,
@@ -3425,7 +3425,8 @@ void X86DAGToDAGISel::Select(SDNode *Nod
// For example, convert "testl %eax, $8" to "testb %al, $8"
VT = MVT::i8;
SubRegOp = X86::sub_8bit;
- Op = X86::TEST8ri;
+ ROpc = X86::TEST8ri;
+ MOpc = X86::TEST8mi;
} else if (OptForMinSize && isUInt<16>(Mask) &&
(!(Mask & 0x8000) || CmpVT == MVT::i16 ||
hasNoSignedComparisonUses(Node))) {
@@ -3435,7 +3436,8 @@ void X86DAGToDAGISel::Select(SDNode *Nod
// changing prefix penalty in the decoders.
VT = MVT::i16;
SubRegOp = X86::sub_16bit;
- Op = X86::TEST16ri;
+ ROpc = X86::TEST16ri;
+ MOpc = X86::TEST16mi;
} else if (isUInt<32>(Mask) && N0.getValueType() != MVT::i16 &&
(!(Mask & 0x80000000) || CmpVT == MVT::i32 ||
hasNoSignedComparisonUses(Node))) {
@@ -3446,7 +3448,8 @@ void X86DAGToDAGISel::Select(SDNode *Nod
// they had a good reason not to and do not promote here.
VT = MVT::i32;
SubRegOp = X86::sub_32bit;
- Op = X86::TEST32ri;
+ ROpc = X86::TEST32ri;
+ MOpc = X86::TEST32mi;
} else {
// No eligible transformation was found.
break;
@@ -3457,12 +3460,25 @@ void X86DAGToDAGISel::Select(SDNode *Nod
SDValue Imm = CurDAG->getTargetConstant(Mask, dl, VT);
SDValue Reg = N0.getOperand(0);
- // Extract the subregister if necessary.
- if (N0.getValueType() != VT)
- Reg = CurDAG->getTargetExtractSubreg(SubRegOp, dl, VT, Reg);
-
// Emit a testl or testw.
- SDNode *NewNode = CurDAG->getMachineNode(Op, dl, MVT::i32, Reg, Imm);
+ MachineSDNode *NewNode;
+ SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
+ if (tryFoldLoad(Node, N0.getNode(), Reg, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) {
+ SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Imm,
+ Reg.getOperand(0) };
+ NewNode = CurDAG->getMachineNode(MOpc, dl, MVT::i32, MVT::Other, Ops);
+ // Update the chain.
+ ReplaceUses(Reg.getValue(1), SDValue(NewNode, 1));
+ // Record the mem-refs
+ CurDAG->setNodeMemRefs(NewNode,
+ {cast<LoadSDNode>(Reg)->getMemOperand()});
+ } else {
+ // Extract the subregister if necessary.
+ if (N0.getValueType() != VT)
+ Reg = CurDAG->getTargetExtractSubreg(SubRegOp, dl, VT, Reg);
+
+ NewNode = CurDAG->getMachineNode(ROpc, dl, MVT::i32, Reg, Imm);
+ }
// Replace CMP with TEST.
ReplaceNode(Node, NewNode);
return;
Modified: llvm/trunk/test/CodeGen/X86/test-shrink.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/test-shrink.ll?rev=343499&r1=343498&r2=343499&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/test-shrink.ll (original)
+++ llvm/trunk/test/CodeGen/X86/test-shrink.ll Mon Oct 1 10:10:50 2018
@@ -645,8 +645,7 @@ define void @and32_trunc_8_sign(i32 %x)
;
; CHECK-X86-LABEL: and32_trunc_8_sign:
; CHECK-X86: # %bb.0:
-; CHECK-X86-NEXT: movl {{[0-9]+}}(%esp), %eax
-; CHECK-X86-NEXT: testb $-128, %al
+; CHECK-X86-NEXT: testb $-128, {{[0-9]+}}(%esp)
; CHECK-X86-NEXT: jg .LBB14_2
; CHECK-X86-NEXT: # %bb.1: # %yes
; CHECK-X86-NEXT: calll bar
@@ -689,8 +688,7 @@ define void @and64_trunc_8_sign(i64 %x)
;
; CHECK-X86-LABEL: and64_trunc_8_sign:
; CHECK-X86: # %bb.0:
-; CHECK-X86-NEXT: movl {{[0-9]+}}(%esp), %eax
-; CHECK-X86-NEXT: testb $-128, %al
+; CHECK-X86-NEXT: testb $-128, {{[0-9]+}}(%esp)
; CHECK-X86-NEXT: jg .LBB15_2
; CHECK-X86-NEXT: # %bb.1: # %yes
; CHECK-X86-NEXT: calll bar
@@ -733,8 +731,7 @@ define void @and32_trunc_16_sign(i32 %x)
;
; CHECK-X86-LABEL: and32_trunc_16_sign:
; CHECK-X86: # %bb.0:
-; CHECK-X86-NEXT: movl {{[0-9]+}}(%esp), %eax
-; CHECK-X86-NEXT: testw $-32768, %ax # imm = 0x8000
+; CHECK-X86-NEXT: testw $-32768, {{[0-9]+}}(%esp) # imm = 0x8000
; CHECK-X86-NEXT: jg .LBB16_2
; CHECK-X86-NEXT: # %bb.1: # %yes
; CHECK-X86-NEXT: calll bar
@@ -777,8 +774,7 @@ define void @and64_trunc_32_sign(i64 %x)
;
; CHECK-X86-LABEL: and64_trunc_32_sign:
; CHECK-X86: # %bb.0:
-; CHECK-X86-NEXT: movl {{[0-9]+}}(%esp), %eax
-; CHECK-X86-NEXT: testw $-32768, %ax # imm = 0x8000
+; CHECK-X86-NEXT: testw $-32768, {{[0-9]+}}(%esp) # imm = 0x8000
; CHECK-X86-NEXT: jg .LBB17_2
; CHECK-X86-NEXT: # %bb.1: # %yes
; CHECK-X86-NEXT: calll bar
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