[llvm] r343484 - [X86][Btver2] Fix BTmr schedule uop counts

[Simon Pilgrim via llvm-commits]

Author: rksimon
Date: Mon Oct  1 07:42:16 2018
New Revision: 343484

URL: http://llvm.org/viewvc/llvm-project?rev=343484&view=rev
Log:
[X86][Btver2] Fix BTmr schedule uop counts

Match AMD Fam16h SOG + llvm-exegesis tests

Modified:
    llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td
    llvm/trunk/test/tools/llvm-mca/X86/BtVer2/resources-x86_64.s

Modified: llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td?rev=343484&r1=343483&r2=343484&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td (original)
+++ llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td Mon Oct  1 07:42:16 2018
@@ -206,7 +206,7 @@ def  : WriteRes<WriteLAHFSAHF, [JALU01]>
 
 defm : X86WriteRes<WriteBitTest,      [JALU01], 1, [1], 1>;
 defm : X86WriteRes<WriteBitTestImmLd, [JALU01, JLAGU], 4, [1, 1], 1>;
-defm : X86WriteRes<WriteBitTestRegLd, [JALU01, JLAGU], 4, [1, 1], 1>;
+defm : X86WriteRes<WriteBitTestRegLd, [JALU01, JLAGU], 4, [1, 1], 5>;
 defm : X86WriteRes<WriteBitTestSet,   [JALU01], 1, [1], 2>;
 
 // This is for simple LEAs with one or two input operands.

Modified: llvm/trunk/test/tools/llvm-mca/X86/BtVer2/resources-x86_64.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/tools/llvm-mca/X86/BtVer2/resources-x86_64.s?rev=343484&r1=343483&r2=343484&view=diff
==============================================================================
--- llvm/trunk/test/tools/llvm-mca/X86/BtVer2/resources-x86_64.s (original)
+++ llvm/trunk/test/tools/llvm-mca/X86/BtVer2/resources-x86_64.s Mon Oct  1 07:42:16 2018
@@ -969,7 +969,7 @@ xorq (%rax), %rdi
 # CHECK-NEXT:  2      1     0.50                        btcw	%si, %di
 # CHECK-NEXT:  2      1     0.50                        btrw	%si, %di
 # CHECK-NEXT:  2      1     0.50                        btsw	%si, %di
-# CHECK-NEXT:  1      4     1.00    *                   btw	%si, (%rax)
+# CHECK-NEXT:  5      4     1.00    *                   btw	%si, (%rax)
 # CHECK-NEXT:  2      4     1.00    *      *            btcw	%si, (%rax)
 # CHECK-NEXT:  2      4     1.00    *      *            btrw	%si, (%rax)
 # CHECK-NEXT:  2      4     1.00    *      *            btsw	%si, (%rax)
@@ -985,7 +985,7 @@ xorq (%rax), %rdi
 # CHECK-NEXT:  2      1     0.50                        btcl	%esi, %edi
 # CHECK-NEXT:  2      1     0.50                        btrl	%esi, %edi
 # CHECK-NEXT:  2      1     0.50                        btsl	%esi, %edi
-# CHECK-NEXT:  1      4     1.00    *                   btl	%esi, (%rax)
+# CHECK-NEXT:  5      4     1.00    *                   btl	%esi, (%rax)
 # CHECK-NEXT:  2      4     1.00    *      *            btcl	%esi, (%rax)
 # CHECK-NEXT:  2      4     1.00    *      *            btrl	%esi, (%rax)
 # CHECK-NEXT:  2      4     1.00    *      *            btsl	%esi, (%rax)
@@ -1001,7 +1001,7 @@ xorq (%rax), %rdi
 # CHECK-NEXT:  2      1     0.50                        btcq	%rsi, %rdi
 # CHECK-NEXT:  2      1     0.50                        btrq	%rsi, %rdi
 # CHECK-NEXT:  2      1     0.50                        btsq	%rsi, %rdi
-# CHECK-NEXT:  1      4     1.00    *                   btq	%rsi, (%rax)
+# CHECK-NEXT:  5      4     1.00    *                   btq	%rsi, (%rax)
 # CHECK-NEXT:  2      4     1.00    *      *            btcq	%rsi, (%rax)
 # CHECK-NEXT:  2      4     1.00    *      *            btrq	%rsi, (%rax)
 # CHECK-NEXT:  2      4     1.00    *      *            btsq	%rsi, (%rax)