[llvm] r343478 - [X86] Create schedule classes for BTmi and BTmr instructions
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Mon Oct 1 07:23:37 PDT 2018
Author: rksimon
Date: Mon Oct 1 07:23:37 2018
New Revision: 343478
URL: http://llvm.org/viewvc/llvm-project?rev=343478&view=rev
Log:
[X86] Create schedule classes for BTmi and BTmr instructions
Modified:
llvm/trunk/lib/Target/X86/X86InstrInfo.td
llvm/trunk/lib/Target/X86/X86SchedBroadwell.td
llvm/trunk/lib/Target/X86/X86SchedHaswell.td
llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td
llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td
llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td
llvm/trunk/lib/Target/X86/X86Schedule.td
llvm/trunk/lib/Target/X86/X86ScheduleAtom.td
llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td
llvm/trunk/lib/Target/X86/X86ScheduleSLM.td
llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td
Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=343478&r1=343477&r2=343478&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Mon Oct 1 07:23:37 2018
@@ -1771,7 +1771,7 @@ def BT64rr : RI<0xA3, MRMDestReg, (outs)
// only for now. These instructions are also slow on modern CPUs so that's
// another reason to avoid generating them.
-let mayLoad = 1, hasSideEffects = 0, SchedRW = [WriteALULd] in {
+let mayLoad = 1, hasSideEffects = 0, SchedRW = [WriteBitTestRegLd] in {
def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
"bt{w}\t{$src2, $src1|$src1, $src2}",
[]>, OpSize16, TB, NotMemoryFoldable;
@@ -1799,7 +1799,7 @@ def BT64ri8 : RIi8<0xBA, MRM4r, (outs),
// Note that these instructions aren't slow because that only applies when the
// other operand is in a register. When it's an immediate, bt is still fast.
-let SchedRW = [WriteALULd] in {
+let SchedRW = [WriteBitTestImmLd] in {
def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
"bt{w}\t{$src2, $src1|$src1, $src2}",
[(set EFLAGS, (X86bt (loadi16 addr:$src1),
Modified: llvm/trunk/lib/Target/X86/X86SchedBroadwell.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedBroadwell.td?rev=343478&r1=343477&r2=343478&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedBroadwell.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedBroadwell.td Mon Oct 1 07:23:37 2018
@@ -161,9 +161,12 @@ def : WriteRes<WriteSETCCStore, [BWPort
let Latency = 2;
let NumMicroOps = 3;
}
-def : WriteRes<WriteLAHFSAHF, [BWPort06]>;
-def : WriteRes<WriteBitTest, [BWPort06]>; // Bit Test instrs
-def : WriteRes<WriteBitTestSet, [BWPort06]>; // Bit Test + Set instrs
+
+defm : X86WriteRes<WriteLAHFSAHF, [BWPort06], 1, [1], 1>;
+defm : X86WriteRes<WriteBitTest, [BWPort06], 1, [1], 1>; // Bit Test instrs
+defm : X86WriteRes<WriteBitTestImmLd, [BWPort06,BWPort23], 6, [1,1], 2>;
+defm : X86WriteRes<WriteBitTestRegLd, [BWPort0156,BWPort23], 6, [1,1], 2>;
+defm : X86WriteRes<WriteBitTestSet, [BWPort06], 1, [1], 1>; // Bit Test + Set instrs
// Bit counts.
defm : BWWriteResPair<WriteBSF, [BWPort1], 3>;
Modified: llvm/trunk/lib/Target/X86/X86SchedHaswell.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedHaswell.td?rev=343478&r1=343477&r2=343478&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedHaswell.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedHaswell.td Mon Oct 1 07:23:37 2018
@@ -165,9 +165,12 @@ def : WriteRes<WriteSETCCStore, [HWPort
let Latency = 2;
let NumMicroOps = 3;
}
-def : WriteRes<WriteLAHFSAHF, [HWPort06]>;
-def : WriteRes<WriteBitTest, [HWPort06]>;
-def : WriteRes<WriteBitTestSet, [HWPort06]>;
+
+defm : X86WriteRes<WriteLAHFSAHF, [HWPort06], 1, [1], 1>;
+defm : X86WriteRes<WriteBitTest, [HWPort06], 1, [1], 1>;
+defm : X86WriteRes<WriteBitTestImmLd, [HWPort06], 1, [1], 1>;
+defm : X86WriteRes<WriteBitTestRegLd, [HWPort06], 1, [1], 1>;
+defm : X86WriteRes<WriteBitTestSet, [HWPort06], 1, [1], 1>;
// This is for simple LEAs with one or two input operands.
// The complex ones can only execute on port 1, and they require two cycles on
Modified: llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td?rev=343478&r1=343477&r2=343478&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td Mon Oct 1 07:23:37 2018
@@ -160,9 +160,12 @@ def : WriteRes<WriteSETCCStore, [SBPort
let Latency = 2;
let NumMicroOps = 3;
}
-def : WriteRes<WriteLAHFSAHF, [SBPort05]>;
-def : WriteRes<WriteBitTest, [SBPort05]>;
-def : WriteRes<WriteBitTestSet, [SBPort05]>;
+
+defm : X86WriteRes<WriteLAHFSAHF, [SBPort05], 1, [1], 1>;
+defm : X86WriteRes<WriteBitTest, [SBPort05], 1, [1], 1>;
+defm : X86WriteRes<WriteBitTestImmLd, [SBPort05], 1, [1], 1>;
+defm : X86WriteRes<WriteBitTestRegLd, [SBPort05], 1, [1], 1>;
+defm : X86WriteRes<WriteBitTestSet, [SBPort05], 1, [1], 1>;
// This is for simple LEAs with one or two input operands.
// The complex ones can only execute on port 1, and they require two cycles on
Modified: llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td?rev=343478&r1=343477&r2=343478&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td Mon Oct 1 07:23:37 2018
@@ -158,9 +158,12 @@ def : WriteRes<WriteSETCCStore, [SKLPor
let Latency = 2;
let NumMicroOps = 3;
}
-def : WriteRes<WriteLAHFSAHF, [SKLPort06]>;
-def : WriteRes<WriteBitTest, [SKLPort06]>;
-def : WriteRes<WriteBitTestSet, [SKLPort06]>;
+
+defm : X86WriteRes<WriteLAHFSAHF, [SKLPort06], 1, [1], 1>;
+defm : X86WriteRes<WriteBitTest, [SKLPort06], 1, [1], 1>;
+defm : X86WriteRes<WriteBitTestImmLd, [SKLPort06,SKLPort23], 6, [1,1], 2>;
+defm : X86WriteRes<WriteBitTestRegLd, [SKLPort0156,SKLPort23], 6, [1,1], 2>;
+defm : X86WriteRes<WriteBitTestSet, [SKLPort06], 1, [1], 1>;
// Bit counts.
defm : SKLWriteResPair<WriteBSF, [SKLPort1], 3>;
Modified: llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td?rev=343478&r1=343477&r2=343478&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td Mon Oct 1 07:23:37 2018
@@ -159,9 +159,11 @@ def : WriteRes<WriteSETCCStore, [SKXPor
let Latency = 2;
let NumMicroOps = 3;
}
-def : WriteRes<WriteLAHFSAHF, [SKXPort06]>;
-def : WriteRes<WriteBitTest, [SKXPort06]>;
-def : WriteRes<WriteBitTestSet, [SKXPort06]>;
+defm : X86WriteRes<WriteLAHFSAHF, [SKXPort06], 1, [1], 1>;
+defm : X86WriteRes<WriteBitTest, [SKXPort06], 1, [1], 1>;
+defm : X86WriteRes<WriteBitTestImmLd, [SKXPort06,SKXPort23], 6, [1,1], 2>;
+defm : X86WriteRes<WriteBitTestRegLd, [SKXPort0156,SKXPort23], 6, [1,1], 2>;
+defm : X86WriteRes<WriteBitTestSet, [SKXPort06], 1, [1], 1>;
// Integer shifts and rotates.
defm : SKXWriteResPair<WriteShift, [SKXPort06], 1>;
Modified: llvm/trunk/lib/Target/X86/X86Schedule.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Schedule.td?rev=343478&r1=343477&r2=343478&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86Schedule.td (original)
+++ llvm/trunk/lib/Target/X86/X86Schedule.td Mon Oct 1 07:23:37 2018
@@ -155,7 +155,11 @@ def WriteFCMOV : SchedWrite; // X87 con
def WriteSETCC : SchedWrite; // Set register based on condition code.
def WriteSETCCStore : SchedWrite;
def WriteLAHFSAHF : SchedWrite; // Load/Store flags in AH.
-def WriteBitTest : SchedWrite; // Bit Test - TODO add memory folding support
+
+def WriteBitTest : SchedWrite; // Bit Test
+def WriteBitTestImmLd : SchedWrite;
+def WriteBitTestRegLd : SchedWrite;
+
def WriteBitTestSet : SchedWrite; // Bit Test + Set - TODO add memory folding support
// Integer shifts and rotates.
Modified: llvm/trunk/lib/Target/X86/X86ScheduleAtom.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ScheduleAtom.td?rev=343478&r1=343477&r2=343478&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ScheduleAtom.td (original)
+++ llvm/trunk/lib/Target/X86/X86ScheduleAtom.td Mon Oct 1 07:23:37 2018
@@ -121,8 +121,10 @@ def : WriteRes<WriteLAHFSAHF, [AtomPort
let Latency = 2;
let ResourceCycles = [2];
}
-defm : X86WriteRes<WriteBitTest, [AtomPort1], 1, [1], 1>;
-defm : X86WriteRes<WriteBitTestSet, [AtomPort1], 1, [1], 1>;
+defm : X86WriteRes<WriteBitTest, [AtomPort1], 1, [1], 1>;
+defm : X86WriteRes<WriteBitTestImmLd, [AtomPort0], 1, [1], 1>;
+defm : X86WriteRes<WriteBitTestRegLd, [AtomPort0], 1, [1], 1>;
+defm : X86WriteRes<WriteBitTestSet, [AtomPort1], 1, [1], 1>;
// This is for simple LEAs with one or two input operands.
def : WriteRes<WriteLEA, [AtomPort1]>;
Modified: llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td?rev=343478&r1=343477&r2=343478&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td (original)
+++ llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td Mon Oct 1 07:23:37 2018
@@ -204,8 +204,10 @@ def : WriteRes<WriteSETCC, [JALU01]>; /
def : WriteRes<WriteSETCCStore, [JALU01,JSAGU]>;
def : WriteRes<WriteLAHFSAHF, [JALU01]>;
-defm : X86WriteRes<WriteBitTest, [JALU01], 1, [1], 1>;
-defm : X86WriteRes<WriteBitTestSet, [JALU01], 1, [1], 2>;
+defm : X86WriteRes<WriteBitTest, [JALU01], 1, [1], 1>;
+defm : X86WriteRes<WriteBitTestImmLd, [JALU01, JLAGU], 4, [1, 1], 1>;
+defm : X86WriteRes<WriteBitTestRegLd, [JALU01, JLAGU], 4, [1, 1], 1>;
+defm : X86WriteRes<WriteBitTestSet, [JALU01], 1, [1], 2>;
// This is for simple LEAs with one or two input operands.
def : WriteRes<WriteLEA, [JALU01]>;
Modified: llvm/trunk/lib/Target/X86/X86ScheduleSLM.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ScheduleSLM.td?rev=343478&r1=343477&r2=343478&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ScheduleSLM.td (original)
+++ llvm/trunk/lib/Target/X86/X86ScheduleSLM.td Mon Oct 1 07:23:37 2018
@@ -134,9 +134,11 @@ def : WriteRes<WriteSETCCStore, [SLM_IE
// FIXME Latency and NumMicrOps?
let ResourceCycles = [2,1];
}
-def : WriteRes<WriteLAHFSAHF, [SLM_IEC_RSV01]>;
-def : WriteRes<WriteBitTest, [SLM_IEC_RSV01]>;
-def : WriteRes<WriteBitTestSet, [SLM_IEC_RSV01]>;
+defm : X86WriteRes<WriteLAHFSAHF, [SLM_IEC_RSV01], 1, [1], 1>;
+defm : X86WriteRes<WriteBitTest, [SLM_IEC_RSV01], 1, [1], 1>;
+defm : X86WriteRes<WriteBitTestImmLd, [SLM_IEC_RSV01, SLM_MEC_RSV], 4, [1,1], 1>;
+defm : X86WriteRes<WriteBitTestRegLd, [SLM_IEC_RSV01, SLM_MEC_RSV], 4, [1,1], 1>;
+defm : X86WriteRes<WriteBitTestSet, [SLM_IEC_RSV01], 1, [1], 1>;
// This is for simple LEAs with one or two input operands.
// The complex ones can only execute on port 1, and they require two cycles on
Modified: llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td?rev=343478&r1=343477&r2=343478&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td (original)
+++ llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td Mon Oct 1 07:23:37 2018
@@ -214,8 +214,10 @@ def : WriteRes<WriteSETCC, [ZnALU]>;
def : WriteRes<WriteSETCCStore, [ZnALU, ZnAGU]>;
defm : X86WriteRes<WriteLAHFSAHF, [ZnALU], 2, [1], 2>;
-defm : X86WriteRes<WriteBitTest, [ZnALU], 1, [1], 1>;
-defm : X86WriteRes<WriteBitTestSet, [ZnALU], 2, [1], 2>;
+defm : X86WriteRes<WriteBitTest, [ZnALU], 1, [1], 1>;
+defm : X86WriteRes<WriteBitTestImmLd, [ZnALU,ZnAGU], 5, [1,1], 2>;
+defm : X86WriteRes<WriteBitTestRegLd, [ZnALU,ZnAGU], 5, [1,1], 2>;
+defm : X86WriteRes<WriteBitTestSet, [ZnALU], 2, [1], 2>;
// Bit counts.
defm : ZnWriteResPair<WriteBSF, [ZnALU], 3>;
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