[PATCH] D52682: [IAI, LV] Avoid creating interleave-groups for predicated accesses

[Dorit Nuzman via Phabricator via llvm-commits]

dorit created this revision.
dorit added reviewers: Ayal, hsaito, dcaballe, fhahn.

This patch fixes PR39099.

When strided loads are predicated, each of them will form an interleaved-group (with gaps). However, subsequent stages of vectorization (planning and transformation) assume that if a load is part of an Interleave-Group it is not predicated, resulting in wrong code - unmasked wide loads are created.

The Interleaving Analysis does take care not to have conditional interleave groups of size > 1, but until we extend the planning and transformation stages to support masked-interleave-groups (I have a patch coming up for that), we should also avoid having them for size == 1.


https://reviews.llvm.org/D52682

Files:
  lib/Analysis/VectorUtils.cpp
  test/Transforms/LoopVectorize/X86/x86-pr39099.ll
  test/Transforms/LoopVectorize/pr39099.ll

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