[PATCH] D52559: [AMDGPU] Divergence driven instruction selection. Shift operations.

[Alexander via Phabricator via llvm-commits]

alex-t added inline comments.


================
Comment at: lib/Target/AMDGPU/VOP3Instructions.td:392
+let SubtargetPredicate = isVI, Predicates = [isVI] in {
+def V_LSHLREV_B64 : VOP3Inst <"v_lshlrev_b64", VOP_PAT_GEN<VOP3_Profile<VOP_I64_I32_I64>>, shl>;
+def V_LSHRREV_B64 : VOP3Inst <"v_lshrrev_b64", VOP_PAT_GEN<VOP3_Profile<VOP_I64_I32_I64>>, srl>;
----------------
rampitec wrote:
> alex-t wrote:
> > rampitec wrote:
> > > It sounds like from your explanation below and the logic of the getVOP3Pat this will create a bogus pattern with wrong operand order. Only one pattern shall exist for (shl i64:x, i32:y) and it seems to be the pattern below. At best this one will never match.
> > If we have VI and only one this:
> > 
> > ```
> > def V_LSHLREV_B64 : VOP3Inst <"v_lshlrev_b64", VOP_PAT_GEN<VOP3_Profile<VOP_I64_I32_I64>>, shl>;
> > 
> > ```
> > then "shl  i64 i32" will never match.
> You have the match for it right below:
> 
>  (getDivergentFrag<shl>.ret i64:$x, i32:$y)
> 
> This is exactly shl i64, i32.
The reason of misunderstanding was that I assumed that it could be

shl i32 i64  input on VI

If it could be we'd really need 2 different patterns for the same instruction V_LSHLREV_B32

one for 
```
shl i32 i64
``` and another for 
```
shl i64 i32
```
```
As soon as I understood that nobody can swap shl dag node operands, everything  become clear.


https://reviews.llvm.org/D52559