[PATCH] D48725: [SLP] Vectorize bit-parallel operations with SWAR.

[Clement Courbet via Phabricator via llvm-commits]

courbet added a comment.

In https://reviews.llvm.org/D48725#1150047, @efriedma wrote:

> > 128 is not the smallest vector, because we can do partial load/stores
>
> Essentially, yes.
>
> > Actually I don't think the current case can be handled in the same way as MatchLoadCombine: in the case the MatchLoadCombine, the "or" instruction provides a way to link the stores together.
>
> We have code to do this sort of merging in DAGCombiner::MergeConsecutiveStores.  But it misses cases like the ones in your patch because combiner-global-alias-analysis is off by default. (I don't remember the full history of that, but IIRC the compile-time penalty was too large.)


Hm actually I had a look at `MergeConsecutiveStores` and it can actually merge non-vector and/or heterogeneous-sized values (https://reviews.llvm.org/D52643). It won't handle my case though because it considers load/store in chain order and considers **any** store to be potentially aliasing the following loads:

This gets merged (the chain is load-load-store-store):

  S PartialCopy(const S& s) {
    S result;
    const auto ta = s.a;
    const auto tb = s.b;
    result.a = ta;
    result.b = tb;
    return result;
  }

But not this (the chain is load-store-load-store):

  S PartialCopy(const S& s) {
    S result;
    result.a = s.a;
    result.b = s.b;
    return result;
  }

Or did I miss something ?


Repository:
  rL LLVM

https://reviews.llvm.org/D48725