[PATCH] D52559: [AMDGPU] Divergence driven instruction selection. Shift operations.

Alexander via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Thu Sep 27 12:32:12 PDT 2018


alex-t added inline comments.


================
Comment at: lib/Target/AMDGPU/VOP3Instructions.td:392
+let SubtargetPredicate = isVI, Predicates = [isVI] in {
+def V_LSHLREV_B64 : VOP3Inst <"v_lshlrev_b64", VOP_PAT_GEN<VOP3_Profile<VOP_I64_I32_I64>>, shl>;
+def V_LSHRREV_B64 : VOP3Inst <"v_lshrrev_b64", VOP_PAT_GEN<VOP3_Profile<VOP_I64_I32_I64>>, srl>;
----------------
rampitec wrote:
> It sounds like from your explanation below and the logic of the getVOP3Pat this will create a bogus pattern with wrong operand order. Only one pattern shall exist for (shl i64:x, i32:y) and it seems to be the pattern below. At best this one will never match.
If we have VI and only one this:

```
def V_LSHLREV_B64 : VOP3Inst <"v_lshlrev_b64", VOP_PAT_GEN<VOP3_Profile<VOP_I64_I32_I64>>, shl>;

```
then "shl  i64 i32" will never match.


https://reviews.llvm.org/D52559





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