[llvm] r343217 - [AArch64][v8.5A] Add Armv8.5-A random number instructions
Oliver Stannard via llvm-commits
llvm-commits at lists.llvm.org
Thu Sep 27 07:01:41 PDT 2018
Author: olista01
Date: Thu Sep 27 07:01:40 2018
New Revision: 343217
URL: http://llvm.org/viewvc/llvm-project?rev=343217&view=rev
Log:
[AArch64][v8.5A] Add Armv8.5-A random number instructions
This adds two new system registers, used to generate random numbers.
This is an optional extension to v8.5-A, and will be controlled by the
"+rng" modifier of the -march= and -mcpu= options.
Patch by Pablo Barrio!
Differential revision: https://reviews.llvm.org/D52481
Added:
llvm/trunk/test/MC/AArch64/armv8.5a-rand-error.s
llvm/trunk/test/MC/AArch64/armv8.5a-rand.s
llvm/trunk/test/MC/Disassembler/AArch64/armv8.5a-rand.txt
Modified:
llvm/trunk/include/llvm/Support/AArch64TargetParser.def
llvm/trunk/include/llvm/Support/TargetParser.h
llvm/trunk/lib/Target/AArch64/AArch64.td
llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h
llvm/trunk/lib/Target/AArch64/AArch64SystemOperands.td
llvm/trunk/unittests/Support/TargetParserTest.cpp
Modified: llvm/trunk/include/llvm/Support/AArch64TargetParser.def
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/AArch64TargetParser.def?rev=343217&r1=343216&r2=343217&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Support/AArch64TargetParser.def (original)
+++ llvm/trunk/include/llvm/Support/AArch64TargetParser.def Thu Sep 27 07:01:40 2018
@@ -70,6 +70,7 @@ AARCH64_ARCH_EXT_NAME("profile", AArch6
AARCH64_ARCH_EXT_NAME("ras", AArch64::AEK_RAS, "+ras", "-ras")
AARCH64_ARCH_EXT_NAME("sve", AArch64::AEK_SVE, "+sve", "-sve")
AARCH64_ARCH_EXT_NAME("rcpc", AArch64::AEK_RCPC, "+rcpc", "-rcpc")
+AARCH64_ARCH_EXT_NAME("rng", AArch64::AEK_RAND, "+rand", "-rand")
#undef AARCH64_ARCH_EXT_NAME
#ifndef AARCH64_CPU_NAME
Modified: llvm/trunk/include/llvm/Support/TargetParser.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/TargetParser.h?rev=343217&r1=343216&r2=343217&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Support/TargetParser.h (original)
+++ llvm/trunk/include/llvm/Support/TargetParser.h Thu Sep 27 07:01:40 2018
@@ -180,6 +180,7 @@ enum ArchExtKind : unsigned {
AEK_SHA2 = 1 << 15,
AEK_AES = 1 << 16,
AEK_FP16FML = 1 << 17,
+ AEK_RAND = 1 << 18,
};
StringRef getCanonicalArchName(StringRef Arch);
Modified: llvm/trunk/lib/Target/AArch64/AArch64.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64.td?rev=343217&r1=343216&r2=343217&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64.td Thu Sep 27 07:01:40 2018
@@ -220,6 +220,9 @@ def FeaturePredCtrl : SubtargetFeature<"
def FeatureCacheDeepPersist : SubtargetFeature<"ccdp", "HasCCDP",
"true", "Enable Cache Clean to Point of Deep Persistence" >;
+def FeatureRandGen : SubtargetFeature<"rand", "HasRandGen",
+ "true", "Enable Random Number generation instructions" >;
+
//===----------------------------------------------------------------------===//
// Architectures.
//
Modified: llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h?rev=343217&r1=343216&r2=343217&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h Thu Sep 27 07:01:40 2018
@@ -100,6 +100,7 @@ protected:
bool HasSpecCtrl = false;
bool HasPredCtrl = false;
bool HasCCDP = false;
+ bool HasRandGen = false;
// HasZeroCycleRegMove - Has zero-cycle register mov instructions.
bool HasZeroCycleRegMove = false;
@@ -318,6 +319,7 @@ public:
bool hasSpecCtrl() { return HasSpecCtrl; }
bool hasPredCtrl() { return HasPredCtrl; }
bool hasCCDP() { return HasCCDP; }
+ bool hasRandGen() { return HasRandGen; }
bool isLittleEndian() const { return IsLittle; }
Modified: llvm/trunk/lib/Target/AArch64/AArch64SystemOperands.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64SystemOperands.td?rev=343217&r1=343216&r2=343217&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64SystemOperands.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64SystemOperands.td Thu Sep 27 07:01:40 2018
@@ -614,6 +614,13 @@ def : ROSysReg<"ERRIDR_EL1", 0b11, 0b000
def : ROSysReg<"ERXFR_EL1", 0b11, 0b000, 0b0101, 0b0100, 0b000>;
}
+// v8.5a "random number" registers
+// Op0 Op1 CRn CRm Op2
+let Requires = [{ {AArch64::FeatureRandGen} }] in {
+def : ROSysReg<"RNDR", 0b11, 0b011, 0b0010, 0b0100, 0b000>;
+def : ROSysReg<"RNDRRS", 0b11, 0b011, 0b0010, 0b0100, 0b001>;
+}
+
//===----------------------
// Write-only regs
//===----------------------
Added: llvm/trunk/test/MC/AArch64/armv8.5a-rand-error.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/armv8.5a-rand-error.s?rev=343217&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/armv8.5a-rand-error.s (added)
+++ llvm/trunk/test/MC/AArch64/armv8.5a-rand-error.s Thu Sep 27 07:01:40 2018
@@ -0,0 +1,17 @@
+// RUN: not llvm-mc -triple aarch64 -show-encoding -mattr=+rand < %s 2>&1| FileCheck %s
+
+mrs rndr
+mrs rndrrs
+
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: rndr
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: rndrrs
+
+mrs rndr, x0
+mrs rndrrs, x1
+
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: rndr
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: rndrrs
Added: llvm/trunk/test/MC/AArch64/armv8.5a-rand.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/armv8.5a-rand.s?rev=343217&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/armv8.5a-rand.s (added)
+++ llvm/trunk/test/MC/AArch64/armv8.5a-rand.s Thu Sep 27 07:01:40 2018
@@ -0,0 +1,14 @@
+// RUN: llvm-mc -triple aarch64 -show-encoding -mattr=+rand < %s | FileCheck %s
+// RUN: not llvm-mc -triple aarch64 -show-encoding -mattr=+v8.5a < %s 2>&1 | FileCheck %s --check-prefix=NORAND
+// RUN: not llvm-mc -triple aarch64 -show-encoding -mattr=-rand < %s 2>&1 | FileCheck %s --check-prefix=NORAND
+
+mrs x0, rndr
+mrs x1, rndrrs
+
+// CHECK: mrs x0, RNDR // encoding: [0x00,0x24,0x3b,0xd5]
+// CHECK: mrs x1, RNDRRS // encoding: [0x21,0x24,0x3b,0xd5]
+
+// NORAND: expected readable system register
+// NORAND-NEXT: rndr
+// NORAND: expected readable system register
+// NORAND-NEXT: rndrrs
Added: llvm/trunk/test/MC/Disassembler/AArch64/armv8.5a-rand.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/AArch64/armv8.5a-rand.txt?rev=343217&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/AArch64/armv8.5a-rand.txt (added)
+++ llvm/trunk/test/MC/Disassembler/AArch64/armv8.5a-rand.txt Thu Sep 27 07:01:40 2018
@@ -0,0 +1,12 @@
+# RUN: llvm-mc -triple=aarch64 -mattr=+rand -disassemble < %s | FileCheck %s
+# RUN: llvm-mc -triple=aarch64 -mattr=+v8.5a -disassemble < %s | FileCheck %s --check-prefix=NORAND
+# RUN: llvm-mc -triple=aarch64 -mattr=-rand -disassemble < %s | FileCheck %s --check-prefix=NORAND
+
+[0x00,0x24,0x3b,0xd5]
+[0x21,0x24,0x3b,0xd5]
+
+# CHECK: mrs x0, RNDR
+# CHECK: mrs x1, RNDRRS
+
+# NORAND: mrs x0, S3_3_C2_C4_0
+# NORAND: mrs x1, S3_3_C2_C4_1
Modified: llvm/trunk/unittests/Support/TargetParserTest.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/unittests/Support/TargetParserTest.cpp?rev=343217&r1=343216&r2=343217&view=diff
==============================================================================
--- llvm/trunk/unittests/Support/TargetParserTest.cpp (original)
+++ llvm/trunk/unittests/Support/TargetParserTest.cpp Thu Sep 27 07:01:40 2018
@@ -967,7 +967,8 @@ TEST(TargetParserTest, AArch64ArchExtFea
{"rdm", "nordm", "+rdm", "-rdm"},
{"sve", "nosve", "+sve", "-sve"},
{"dotprod", "nodotprod", "+dotprod", "-dotprod"},
- {"rcpc", "norcpc", "+rcpc", "-rcpc" }};
+ {"rcpc", "norcpc", "+rcpc", "-rcpc" },
+ {"rng", "norng", "+rand", "-rand"}};
for (unsigned i = 0; i < array_lengthof(ArchExt); i++) {
EXPECT_EQ(StringRef(ArchExt[i][2]),
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