[llvm] r343211 - [AArch64][v8.5A] Add speculation barrier to AArch64 instruction set
Oliver Stannard via llvm-commits
llvm-commits at lists.llvm.org
Thu Sep 27 06:39:06 PDT 2018
Author: olista01
Date: Thu Sep 27 06:39:06 2018
New Revision: 343211
URL: http://llvm.org/viewvc/llvm-project?rev=343211&view=rev
Log:
[AArch64][v8.5A] Add speculation barrier to AArch64 instruction set
This is a new barrier which limits speculative execution of the
instructions following it.
Patch by Pablo Barrio!
Differential revision: https://reviews.llvm.org/D52476
Added:
llvm/trunk/test/MC/AArch64/armv8.5a-specctrl.s
llvm/trunk/test/MC/Disassembler/AArch64/armv8.5a-specctrl.txt
Modified:
llvm/trunk/lib/Target/AArch64/AArch64.td
llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td
llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h
Modified: llvm/trunk/lib/Target/AArch64/AArch64.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64.td?rev=343211&r1=343210&r2=343211&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64.td Thu Sep 27 06:39:06 2018
@@ -211,6 +211,9 @@ def FeatureFRInt3264 : SubtargetFeature<
"Enable FRInt[32|64][Z|X] instructions that round a floating-point number to "
"an integer (in FP format) forcing it to fit into a 32- or 64-bit int" >;
+def FeatureSpecCtrl : SubtargetFeature<"specctrl", "HasSpecCtrl", "true",
+ "Enable speculation control barrier" >;
+
//===----------------------------------------------------------------------===//
// Architectures.
//
@@ -229,7 +232,7 @@ def HasV8_4aOps : SubtargetFeature<"v8.4
def HasV8_5aOps : SubtargetFeature<
"v8.5a", "HasV8_5aOps", "true", "Support ARM v8.5a instructions",
- [HasV8_4aOps, FeatureAltFPCmp, FeatureFRInt3264]
+ [HasV8_4aOps, FeatureAltFPCmp, FeatureFRInt3264, FeatureSpecCtrl]
>;
//===----------------------------------------------------------------------===//
Modified: llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td?rev=343211&r1=343210&r2=343211&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td Thu Sep 27 06:39:06 2018
@@ -66,6 +66,8 @@ def HasAltNZCV : Predicate<"Subtar
AssemblerPredicate<"FeatureAltFPCmp", "altnzcv">;
def HasFRInt3264 : Predicate<"Subtarget->hasFRInt3264()">,
AssemblerPredicate<"FeatureFRInt3264", "frint3264">;
+def HasSpecCtrl : Predicate<"Subtarget->hasSpecCtrl()">,
+ AssemblerPredicate<"FeatureSpecCtrl", "specctrl">;
def IsLE : Predicate<"Subtarget->isLittleEndian()">;
def IsBE : Predicate<"!Subtarget->isLittleEndian()">;
def UseAlternateSExtLoadCVTF32
@@ -627,9 +629,17 @@ def AXFLAG : PstateWriteSimple<(ins), "a
let Unpredictable{11-8} = 0b1111;
let Inst{7-5} = 0b010;
}
-
} // HasAltNZCV
+
+// Armv8.5-A speculation barrier
+def SB : SimpleSystemI<0, (ins), "sb", "">, Sched<[]> {
+ let Inst{20-5} = 0b0001100110000111;
+ let Unpredictable{11-8} = 0b1111;
+ let Predicates = [HasSpecCtrl];
+ let hasSideEffects = 1;
+}
+
def : InstAlias<"clrex", (CLREX 0xf)>;
def : InstAlias<"isb", (ISB 0xf)>;
Modified: llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h?rev=343211&r1=343210&r2=343211&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h Thu Sep 27 06:39:06 2018
@@ -97,6 +97,7 @@ protected:
// Armv8.5-A Extensions
bool HasAlternativeNZCV = false;
bool HasFRInt3264 = false;
+ bool HasSpecCtrl = false;
// HasZeroCycleRegMove - Has zero-cycle register mov instructions.
bool HasZeroCycleRegMove = false;
@@ -312,6 +313,7 @@ public:
bool hasAggressiveFMA() const { return HasAggressiveFMA; }
bool hasAlternativeNZCV() const { return HasAlternativeNZCV; }
bool hasFRInt3264() const { return HasFRInt3264; }
+ bool hasSpecCtrl() { return HasSpecCtrl; }
bool isLittleEndian() const { return IsLittle; }
Added: llvm/trunk/test/MC/AArch64/armv8.5a-specctrl.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/armv8.5a-specctrl.s?rev=343211&view=auto
==============================================================================
--- llvm/trunk/test/MC/AArch64/armv8.5a-specctrl.s (added)
+++ llvm/trunk/test/MC/AArch64/armv8.5a-specctrl.s Thu Sep 27 06:39:06 2018
@@ -0,0 +1,11 @@
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+specctrl < %s | FileCheck %s
+// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.5a < %s | FileCheck %s
+// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=-specctrl < %s 2>&1 | FileCheck %s --check-prefix=NOSB
+
+// Flag manipulation
+sb
+
+// CHECK: sb // encoding: [0xff,0x30,0x03,0xd5]
+
+// NOSB: instruction requires: specctrl
+// NOSB-NEXT: sb
Added: llvm/trunk/test/MC/Disassembler/AArch64/armv8.5a-specctrl.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/AArch64/armv8.5a-specctrl.txt?rev=343211&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/AArch64/armv8.5a-specctrl.txt (added)
+++ llvm/trunk/test/MC/Disassembler/AArch64/armv8.5a-specctrl.txt Thu Sep 27 06:39:06 2018
@@ -0,0 +1,9 @@
+# RUN: llvm-mc -triple=aarch64-none-linux-gnu -mattr=+specctrl -disassemble < %s | FileCheck %s
+# RUN: llvm-mc -triple=aarch64-none-linux-gnu -mattr=+v8.5a -disassemble < %s | FileCheck %s
+# RUN: llvm-mc -triple=aarch64-none-linux-gnu -mattr=-specctrl -disassemble < %s 2>&1 | FileCheck %s --check-prefix=NOSB
+
+# New reg
+0xff 0x30 0x03 0xd5
+
+# CHECK: sb
+# NOSB: msr S0_3_C3_C0_7, xzr
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