[PATCH] D52559: [AMDGPU] Divergence driven instruction selection. Shift operations.

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec added inline comments.


================
Comment at: lib/Target/AMDGPU/VOP3Instructions.td:399
+let Predicates = [isVI] in {
+def : AMDGPUPat <
+ (shl i64:$x, i32:$y),
----------------
Why not GCNPat?
Why divergence is not checked?
Why do you need it at all if you have patgen enabled for these instructions above?


================
Comment at: lib/Target/AMDGPU/VOP3Instructions.td:587
+    VOP3e_si <op, !cast<VOP3_Pseudo>(NAME).Pfl> {
+      // Hack to stop printing _e64
+      VOP3_Pseudo ps = !cast<VOP3_Pseudo>(NAME);
----------------
Does it really belong to this patch?


Repository:
  rL LLVM

https://reviews.llvm.org/D52559