[PATCH] D50977: [TableGen] Prefer user-defined subregister compositions over inferred ones

[Bjorn Pettersson via Phabricator via llvm-commits]

bjope added a comment.

The  FPR64 and VR128 classes are a little bit unusual(?) as they only have one subreg, that maps to the high part of the register.

For VR128 (that isn't `CoveredBySubregs` only the high part should be accessible using subregs afaict. So it should not be possible to do `subreg_h32(V0)`, right?
To be able to access bit 32-63 you need to say that VR128 has two subregs,`SubRegIndices = [subreg_h32, subreg_h64]`.


Repository:
  rL LLVM

https://reviews.llvm.org/D50977