[llvm] r343101 - [DAG] ExpandLegalINT_TO_FP - pull out repeated getValueType() call. NFCI.
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Wed Sep 26 05:42:20 PDT 2018
Author: rksimon
Date: Wed Sep 26 05:42:19 2018
New Revision: 343101
URL: http://llvm.org/viewvc/llvm-project?rev=343101&view=rev
Log:
[DAG] ExpandLegalINT_TO_FP - pull out repeated getValueType() call. NFCI.
Modified:
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=343101&r1=343100&r2=343101&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Wed Sep 26 05:42:19 2018
@@ -2301,9 +2301,11 @@ SelectionDAGLegalize::ExpandSinCosLibCal
SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned, SDValue Op0,
EVT DestVT,
const SDLoc &dl) {
+ EVT SrcVT = Op0.getValueType();
+
// TODO: Should any fast-math-flags be set for the created nodes?
LLVM_DEBUG(dbgs() << "Legalizing INT_TO_FP\n");
- if (Op0.getValueType() == MVT::i32 && TLI.isTypeLegal(MVT::f64)) {
+ if (SrcVT == MVT::i32 && TLI.isTypeLegal(MVT::f64)) {
LLVM_DEBUG(dbgs() << "32-bit [signed|unsigned] integer to float/double "
"expansion\n");
@@ -2369,7 +2371,7 @@ SDValue SelectionDAGLegalize::ExpandLega
// of performing rounding correctly, both in the default rounding mode
// and in all alternate rounding modes.
// TODO: Generalize this for use with other types.
- if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f64) {
+ if (SrcVT == MVT::i64 && DestVT == MVT::f64) {
LLVM_DEBUG(dbgs() << "Converting unsigned i64 to f64\n");
SDValue TwoP52 =
DAG.getConstant(UINT64_C(0x4330000000000000), dl, MVT::i64);
@@ -2392,7 +2394,7 @@ SDValue SelectionDAGLegalize::ExpandLega
}
// TODO: Generalize this for use with other types.
- if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f32) {
+ if (SrcVT == MVT::i64 && DestVT == MVT::f32) {
LLVM_DEBUG(dbgs() << "Converting unsigned i64 to f32\n");
// For unsigned conversions, convert them to signed conversions using the
// algorithm from the x86_64 __floatundidf in compiler_rt.
@@ -2400,7 +2402,7 @@ SDValue SelectionDAGLegalize::ExpandLega
SDValue Fast = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Op0);
SDValue ShiftConst = DAG.getConstant(
- 1, dl, TLI.getShiftAmountTy(Op0.getValueType(), DAG.getDataLayout()));
+ 1, dl, TLI.getShiftAmountTy(SrcVT, DAG.getDataLayout()));
SDValue Shr = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0, ShiftConst);
SDValue AndConst = DAG.getConstant(1, dl, MVT::i64);
SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0, AndConst);
@@ -2454,10 +2456,8 @@ SDValue SelectionDAGLegalize::ExpandLega
SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0);
- SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(Op0.getValueType()),
- Op0,
- DAG.getConstant(0, dl, Op0.getValueType()),
- ISD::SETLT);
+ SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(SrcVT), Op0,
+ DAG.getConstant(0, dl, SrcVT), ISD::SETLT);
SDValue Zero = DAG.getIntPtrConstant(0, dl),
Four = DAG.getIntPtrConstant(4, dl);
SDValue CstOffset = DAG.getSelect(dl, Zero.getValueType(),
@@ -2467,7 +2467,7 @@ SDValue SelectionDAGLegalize::ExpandLega
// as a negative number. To counteract this, the dynamic code adds an
// offset depending on the data type.
uint64_t FF;
- switch (Op0.getSimpleValueType().SimpleTy) {
+ switch (SrcVT.getSimpleVT().SimpleTy) {
default: llvm_unreachable("Unsupported integer type!");
case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
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