[PATCH] D52541: [X86][Sched] Update scheduling information for VZEROALL on Haswell.
Clement Courbet via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Sep 26 04:29:42 PDT 2018
courbet created this revision.
courbet added reviewers: craig.topper, RKSimon.
While looking at PR35606, I found out that the scheduling info is incorrect.
One can check that it's really a https://reviews.llvm.org/P5+https://reviews.llvm.org/P6 and not a 2*https://reviews.llvm.org/P56 with:
echo -e 'vzeroall\nvandps %xmm1, %xmm2, %xmm3' | ./bin/llvm-exegesis -mode=uops -snippets-file=-
(vandps executes on https://reviews.llvm.org/P5 only)
Repository:
rL LLVM
https://reviews.llvm.org/D52541
Files:
lib/Target/X86/X86SchedHaswell.td
Index: lib/Target/X86/X86SchedHaswell.td
===================================================================
--- lib/Target/X86/X86SchedHaswell.td
+++ lib/Target/X86/X86SchedHaswell.td
@@ -1616,10 +1616,10 @@
}
def: InstRW<[HWWriteResGroup144], (instrs INSB, INSL, INSW)>;
-def HWWriteResGroup145 : SchedWriteRes<[HWPort5]> {
- let Latency = 16;
- let NumMicroOps = 16;
- let ResourceCycles = [16];
+def HWWriteResGroup145 : SchedWriteRes<[HWPort5, HWPort6]> {
+ let Latency = 8;
+ let NumMicroOps = 20;
+ let ResourceCycles = [1,1];
}
def: InstRW<[HWWriteResGroup145], (instrs VZEROALL)>;
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