[PATCH] D52426: [X86] Move X86DAGToDAGISel::matchBEXTRFromAnd() into X86ISelLowering

[Roman Lebedev via Phabricator via llvm-commits]

lebedev.ri added a comment.

In https://reviews.llvm.org/D52426#1246032, @craig.topper wrote:

> We'd only be ok with BEXTRI TBM instruction.
>  I'm not sure matchBEXTRFromAnd() for BMI was ever a good idea for Intel CPUs. I took it out and got performance improvements on several benchmarks in our internal list. Only a couple regressions and one of those was on a test that's really sensitive to code layout.
>  In the case from PR38938 we were able to fold the shl into an addressing calculation which made it beneficial.


Okay, so these simple cases are ok if there is TBM.
But the PR38938 - AMD Jaguar - does not have TBM.
There really isn't any fundamental difference in the IR between this, and the https://reviews.llvm.org/D52293,
so i would have guessed they should be using the *same* profitability check, correct?
So what would it be? "have TBM, or shifting a newly-loaded value?"
@RKSimon


Repository:
  rL LLVM

https://reviews.llvm.org/D52426