[PATCH] D52518: AMDGPU: Add Selection patterns to support add of one bit.

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added a comment.

Also needs to support/test sub. I’m also concerned it’s not this simple with i1 to use a scalar operation. This needs some tests stressing SIFixSGPRCopies, and with control flow


Repository:
  rL LLVM

https://reviews.llvm.org/D52518