[llvm] r343030 - AMDGPU: Add Selection patterns to support add of one bit.
Changpeng Fang via llvm-commits
llvm-commits at lists.llvm.org
Tue Sep 25 14:21:18 PDT 2018
Author: chfang
Date: Tue Sep 25 14:21:18 2018
New Revision: 343030
URL: http://llvm.org/viewvc/llvm-project?rev=343030&view=rev
Log:
AMDGPU: Add Selection patterns to support add of one bit.
Summary:
We generate s_xor to lower add of i1s in general cases, and s_not to
lower add with a one-bit imm of -1 (true).
Reviewers:
rampitec
Differential Revision:
https://reviews.llvm.org/D52518
Added:
llvm/trunk/test/CodeGen/AMDGPU/add_i1.ll
Modified:
llvm/trunk/lib/Target/AMDGPU/SIInstructions.td
Modified: llvm/trunk/lib/Target/AMDGPU/SIInstructions.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInstructions.td?rev=343030&r1=343029&r2=343030&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIInstructions.td (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIInstructions.td Tue Sep 25 14:21:18 2018
@@ -1323,6 +1323,18 @@ def : GCNPat <
>;
def : GCNPat <
+ (i1 (add i1:$src0, i1:$src1)),
+ (S_XOR_B64 $src0, $src1)
+>;
+
+let AddedComplexity = 1 in {
+def : GCNPat <
+ (i1 (add i1:$src0, (i1 -1))),
+ (S_NOT_B64 $src0)
+>;
+}
+
+def : GCNPat <
(f16 (sint_to_fp i1:$src)),
(V_CVT_F16_F32_e32 (V_CNDMASK_B32_e64 (i32 0), (i32 CONST.FP32_NEG_ONE), $src))
>;
Added: llvm/trunk/test/CodeGen/AMDGPU/add_i1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/add_i1.ll?rev=343030&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/add_i1.ll (added)
+++ llvm/trunk/test/CodeGen/AMDGPU/add_i1.ll Tue Sep 25 14:21:18 2018
@@ -0,0 +1,21 @@
+; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
+
+
+; GCN-LABEL: {{^}}add_var_var_i1:
+; GCN: s_xor_b64
+define amdgpu_kernel void @add_var_var_i1(i1 addrspace(1)* %out, i1 addrspace(1)* %in0, i1 addrspace(1)* %in1) {
+ %a = load volatile i1, i1 addrspace(1)* %in0
+ %b = load volatile i1, i1 addrspace(1)* %in1
+ %add = add i1 %a, %b
+ store i1 %add, i1 addrspace(1)* %out
+ ret void
+}
+
+; GCN-LABEL: {{^}}add_var_imm_i1:
+; GCN: s_not_b64
+define amdgpu_kernel void @add_var_imm_i1(i1 addrspace(1)* %out, i1 addrspace(1)* %in) {
+ %a = load volatile i1, i1 addrspace(1)* %in
+ %add = add i1 %a, 1
+ store i1 %add, i1 addrspace(1)* %out
+ ret void
+}
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