[PATCH] D52387: [WebAssembly] SIMD sqrt
Thomas Lively via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Sep 24 20:42:17 PDT 2018
This revision was automatically updated to reflect the committed changes.
Closed by commit rL342937: [WebAssembly] SIMD sqrt (authored by tlively, committed by ).
Repository:
rL LLVM
https://reviews.llvm.org/D52387
Files:
llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
llvm/trunk/test/CodeGen/WebAssembly/simd-arith.ll
llvm/trunk/test/MC/WebAssembly/simd-encodings.s
Index: llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
===================================================================
--- llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
+++ llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
@@ -212,6 +212,12 @@
[(set (vec_t V128:$dst), (vec_t (fabs V128:$vec)))],
vec#".abs\t$dst, $vec", vec#".abs", simdop>;
}
+multiclass SIMDSqrt<ValueType vec_t, string vec, bits<32> simdop> {
+ defm SQRT_#vec_t :
+ SIMD_I<(outs V128:$dst), (ins V128:$vec), (outs), (ins),
+ [(set (vec_t V128:$dst), (vec_t (fsqrt V128:$vec)))],
+ vec#".sqrt\t$dst, $vec", vec#".sqrt", simdop>;
+}
let Defs = [ARGUMENTS] in {
defm "" : ConstVec<v16i8,
@@ -371,6 +377,9 @@
defm "" : SIMDAbs<v4f32, "f32x4", 127>;
defm "" : SIMDAbs<v2f64, "f64x2", 128>;
+defm "" : SIMDSqrt<v4f32, "f32x4", 141>;
+defm "" : SIMDSqrt<v2f64, "f64x2", 142>;
+
} // Defs = [ARGUMENTS]
// Def load and store patterns from WebAssemblyInstrMemory.td for vector types
Index: llvm/trunk/test/CodeGen/WebAssembly/simd-arith.ll
===================================================================
--- llvm/trunk/test/CodeGen/WebAssembly/simd-arith.ll
+++ llvm/trunk/test/CodeGen/WebAssembly/simd-arith.ll
@@ -723,6 +723,18 @@
ret <4 x float> %a
}
+; CHECK-LABEL: sqrt_v4f32:
+; NO-SIMD128-NOT: f32x4
+; SIMD128-NEXT: .param v128{{$}}
+; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: f32x4.sqrt $push[[R:[0-9]+]]=, $0{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+declare <4 x float> @llvm.sqrt.v4f32(<4 x float> %x)
+define <4 x float> @sqrt_v4f32(<4 x float> %x) {
+ %a = call <4 x float> @llvm.sqrt.v4f32(<4 x float> %x)
+ ret <4 x float> %a
+}
+
; ==============================================================================
; 2 x double
; ==============================================================================
@@ -797,3 +809,15 @@
%a = fmul <2 x double> %x, %y
ret <2 x double> %a
}
+
+; CHECK-LABEL: sqrt_v2f64:
+; NO-SIMD128-NOT: f64x2
+; SIMD128-NEXT: .param v128{{$}}
+; SIMD128-NEXT: .result v128{{$}}
+; SIMD128-NEXT: f64x2.sqrt $push[[R:[0-9]+]]=, $0{{$}}
+; SIMD128-NEXT: return $pop[[R]]{{$}}
+declare <2 x double> @llvm.sqrt.v2f64(<2 x double> %x)
+define <2 x double> @sqrt_v2f64(<2 x double> %x) {
+ %a = call <2 x double> @llvm.sqrt.v2f64(<2 x double> %x)
+ ret <2 x double> %a
+}
Index: llvm/trunk/test/MC/WebAssembly/simd-encodings.s
===================================================================
--- llvm/trunk/test/MC/WebAssembly/simd-encodings.s
+++ llvm/trunk/test/MC/WebAssembly/simd-encodings.s
@@ -355,4 +355,10 @@
# CHECK: f64x2.mul # encoding: [0xfd,0x8c]
f64x2.mul
+ # CHECK: f32x4.sqrt # encoding: [0xfd,0x8d]
+ f32x4.sqrt
+
+ # CHECK: f64x2.sqrt # encoding: [0xfd,0x8e]
+ f64x2.sqrt
+
end_function
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