[PATCH] D52325: [WebAssembly] SIMD min and max

[Thomas Lively via Phabricator via llvm-commits]

tlively added a comment.

In https://reviews.llvm.org/D52325#1244023, @aheejin wrote:

> What happens if we use ordered comparisons? They fail to be selected?


I would expect ordered comparisons to lower to fminnan/fmaxnan if the constant vector was on the left hand side and the variable vector was on the right hand side. That way, any NaNs in the variable vector would compare as `false` and then be returned when the select chooses the right hand side.


Repository:
  rL LLVM

https://reviews.llvm.org/D52325