[llvm] r342847 - Fix line ending mismatches. NFCI.

Simon Pilgrim via llvm-commits llvm-commits at lists.llvm.org
Sun Sep 23 12:16:32 PDT 2018


Author: rksimon
Date: Sun Sep 23 12:16:32 2018
New Revision: 342847

URL: http://llvm.org/viewvc/llvm-project?rev=342847&view=rev
Log:
Fix line ending mismatches. NFCI.

Modified:
    llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td

Modified: llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td?rev=342847&r1=342846&r2=342847&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td Sun Sep 23 12:16:32 2018
@@ -1118,12 +1118,12 @@ def SBWriteResGroup106 : SchedWriteRes<[
 }
 def: InstRW<[SBWriteResGroup106], (instregex "FICOM(P?)(16|32)m")>;
 
-def SBWriteResGroup108 : SchedWriteRes<[SBPort05,SBPort23]> {
-  let Latency = 11;
-  let NumMicroOps = 11;
-  let ResourceCycles = [7,4];
-}
-def: InstRW<[SBWriteResGroup108], (instregex "RCL(8|16|32|64)m",
+def SBWriteResGroup108 : SchedWriteRes<[SBPort05,SBPort23]> {
+  let Latency = 11;
+  let NumMicroOps = 11;
+  let ResourceCycles = [7,4];
+}
+def: InstRW<[SBWriteResGroup108], (instregex "RCL(8|16|32|64)m",
                                              "RCR(8|16|32|64)m")>;
 
 def SBWriteResGroup111 : SchedWriteRes<[SBPort0,SBPort23]> {




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