[llvm] r342841 - [X86] Remove unnecessary WriteRotate overrides. NFCI.

[Simon Pilgrim via llvm-commits]

Author: rksimon
Date: Sun Sep 23 09:53:02 2018
New Revision: 342841

URL: http://llvm.org/viewvc/llvm-project?rev=342841&view=rev
Log:
[X86] Remove unnecessary WriteRotate overrides. NFCI.

Modified:
    llvm/trunk/lib/Target/X86/X86SchedBroadwell.td
    llvm/trunk/lib/Target/X86/X86SchedHaswell.td
    llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td
    llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td

Modified: llvm/trunk/lib/Target/X86/X86SchedBroadwell.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedBroadwell.td?rev=342841&r1=342840&r2=342841&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedBroadwell.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedBroadwell.td Sun Sep 23 09:53:02 2018
@@ -151,7 +151,7 @@ defm : BWWriteResPair<WritePOPCNT,
 
 // Integer shifts and rotates.
 defm : BWWriteResPair<WriteShift,  [BWPort06],  1>;
-defm : BWWriteResPair<WriteRotate, [BWPort06],  1>;
+defm : BWWriteResPair<WriteRotate, [BWPort06],  2, [2], 2>;
 
 // SHLD/SHRD.
 defm : X86WriteRes<WriteSHDrri, [BWPort1], 3, [1], 1>;
@@ -650,14 +650,6 @@ def BWWriteResGroup12 : SchedWriteRes<[B
 }
 def: InstRW<[BWWriteResGroup12], (instrs FDECSTP)>;
 
-def BWWriteResGroup13 : SchedWriteRes<[BWPort06]> {
-  let Latency = 2;
-  let NumMicroOps = 2;
-  let ResourceCycles = [2];
-}
-def: InstRW<[BWWriteResGroup13], (instregex "ROL(8|16|32|64)r(1|i)",
-                                            "ROR(8|16|32|64)r(1|i)")>;
-
 def BWWriteResGroup14 : SchedWriteRes<[BWPort0156]> {
   let Latency = 2;
   let NumMicroOps = 2;

Modified: llvm/trunk/lib/Target/X86/X86SchedHaswell.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedHaswell.td?rev=342841&r1=342840&r2=342841&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedHaswell.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedHaswell.td Sun Sep 23 09:53:02 2018
@@ -134,7 +134,7 @@ def  : WriteRes<WriteIMulH, []> { let La
 
 // Integer shifts and rotates.
 defm : HWWriteResPair<WriteShift,  [HWPort06],  1>;
-defm : HWWriteResPair<WriteRotate, [HWPort06],  1>;
+defm : HWWriteResPair<WriteRotate, [HWPort06],  2, [2], 2>;
 
 // SHLD/SHRD.
 defm : X86WriteRes<WriteSHDrri, [HWPort1], 3, [1], 1>;
@@ -1101,14 +1101,6 @@ def HWWriteResGroup28 : SchedWriteRes<[H
 }
 def: InstRW<[HWWriteResGroup28], (instrs FDECSTP)>;
 
-def HWWriteResGroup29 : SchedWriteRes<[HWPort06]> {
-  let Latency = 2;
-  let NumMicroOps = 2;
-  let ResourceCycles = [2];
-}
-def: InstRW<[HWWriteResGroup29], (instregex "ROL(8|16|32|64)r(1|i)",
-                                            "ROR(8|16|32|64)r(1|i)")>;
-
 def HWWriteResGroup30 : SchedWriteRes<[HWPort0156]> {
   let Latency = 2;
   let NumMicroOps = 2;

Modified: llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td?rev=342841&r1=342840&r2=342841&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td Sun Sep 23 09:53:02 2018
@@ -150,7 +150,7 @@ defm : SKLWriteResPair<WritePOPCNT,
 
 // Integer shifts and rotates.
 defm : SKLWriteResPair<WriteShift,  [SKLPort06],  1>;
-defm : SKLWriteResPair<WriteRotate, [SKLPort06],  1>;
+defm : SKLWriteResPair<WriteRotate, [SKLPort06],  2, [2], 2>;
 
 // SHLD/SHRD.
 defm : X86WriteRes<WriteSHDrri, [SKLPort1], 3, [1], 1>;
@@ -669,9 +669,7 @@ def SKLWriteResGroup15 : SchedWriteRes<[
   let NumMicroOps = 2;
   let ResourceCycles = [2];
 }
-def: InstRW<[SKLWriteResGroup15], (instregex "ROL(8|16|32|64)r(1|i)",
-                                             "ROR(8|16|32|64)r(1|i)",
-                                             "SET(A|BE)r")>;
+def: InstRW<[SKLWriteResGroup15], (instregex "SET(A|BE)r")>;
 
 def SKLWriteResGroup17 : SchedWriteRes<[SKLPort0156]> {
   let Latency = 2;

Modified: llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td?rev=342841&r1=342840&r2=342841&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td Sun Sep 23 09:53:02 2018
@@ -143,7 +143,7 @@ def  : WriteRes<WriteBitTest,  [SKXPort0
 
 // Integer shifts and rotates.
 defm : SKXWriteResPair<WriteShift,  [SKXPort06],  1>;
-defm : SKXWriteResPair<WriteRotate, [SKXPort06],  1>;
+defm : SKXWriteResPair<WriteRotate, [SKXPort06],  2, [2], 2>;
 
 // SHLD/SHRD.
 defm : X86WriteRes<WriteSHDrri, [SKXPort1], 3, [1], 1>;
@@ -693,9 +693,7 @@ def SKXWriteResGroup15 : SchedWriteRes<[
   let NumMicroOps = 2;
   let ResourceCycles = [2];
 }
-def: InstRW<[SKXWriteResGroup15], (instregex "ROL(8|16|32|64)r(1|i)",
-                                             "ROR(8|16|32|64)r(1|i)",
-                                             "SET(A|BE)r")>;
+def: InstRW<[SKXWriteResGroup15], (instregex "SET(A|BE)r")>;
 
 def SKXWriteResGroup17 : SchedWriteRes<[SKXPort0156]> {
   let Latency = 2;