[PATCH] D52358: [X86][Sched] Add zero idiom sched data to the SNB model.

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added a comment.

In https://reviews.llvm.org/D52358#1241869, @courbet wrote:

> I'd also like to get you opinion on whether we should assume that these apply to, e.g. VXORPDYrr. Because SNB is the default model, I think it would make sense to do it if typical CPU support it.


The model has to match that cpu architecture - "supporting" additional instructions is one thing, but otherwise I'd say we need to match what Agner/Intel say.

Oddly, the Intel AoM mentions VXORPS/PD xmm and ymm and but not VANDNPS/PD as a dependency breaking zero idiom @craig.topper Any thoughts?


Repository:
  rL LLVM

https://reviews.llvm.org/D52358