[PATCH] D52358: [X86][Sched] Add zero idiom sched data to the SNB model.
Clement Courbet via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Sep 21 06:52:23 PDT 2018
courbet added a comment.
I'd also like to get you opinion on whether we should assume that these apply to, e.g. VXORPDYrr. Because SNB is the default model, I think it would make sense to do it if typical CPU support it.
For example it's the case for HSW and SKL/SKX:
echo 'vxorps %ymm0, %ymm0, %ymm1' | llvm-exegesis -mode=uops -snippets-file=-
---
mode: uops
key:
instructions:
- 'VXORPSYrr YMM1 YMM0 YMM0'
config: ''
cpu_name: haswell
llvm_triple: x86_64-grtev4-linux-gnu
num_repetitions: 10000
measurements:
- { key: '3', value: 0.0008, debug_string: HWPort0 }
- { key: '4', value: 0.0012, debug_string: HWPort1 }
- { key: '5', value: 0.0006, debug_string: HWPort2 }
- { key: '6', value: 0.0003, debug_string: HWPort3 }
- { key: '7', value: 0.0002, debug_string: HWPort4 }
- { key: '8', value: 0.0009, debug_string: HWPort5 }
- { key: '9', value: 0.0028, debug_string: HWPort6 }
- { key: '10', value: 0.0001, debug_string: HWPort7 }
error: ''
info: ''
assembled_snippet: C5FC57C8C5FC57C8C5FC57C8C5FC57C8C5FC57C8C5FC57C8C5FC57C8C5FC57C8C5FC57C8C5FC57C8C5FC57C8C5FC57C8C5FC57C8C5FC57C8C5FC57C8C5FC57C8C3
...
Repository:
rL LLVM
https://reviews.llvm.org/D52358
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