[llvm] r342611 - [PowerPC] Fix the assert of combineBVOfConsecutiveLoads when element num is 1

[QingShan Zhang via llvm-commits]

Author: qshanz
Date: Wed Sep 19 20:09:15 2018
New Revision: 342611

URL: http://llvm.org/viewvc/llvm-project?rev=342611&view=rev
Log:
[PowerPC] Fix the assert of combineBVOfConsecutiveLoads when element num is 1
Building a vector out of multiple loads can be converted to a load of the vector type if the loads are consecutive.
But the special condition is that the element number is 1, such as <1 x i128>. So just early exit to fix the assert.

Patch By: wuzish (Zixuan Wu)
Differential Revision: https://reviews.llvm.org/D52072

Modified:
    llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
    llvm/trunk/test/CodeGen/PowerPC/crash.ll

Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=342611&r1=342610&r2=342611&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Wed Sep 19 20:09:15 2018
@@ -11901,7 +11901,8 @@ static SDValue combineBVOfConsecutiveLoa
     IsRoundOfExtLoad = LD->getExtensionType() == ISD::EXTLOAD;
   }
   // Not a build vector of (possibly fp_rounded) loads.
-  if (!IsRoundOfExtLoad && FirstInput.getOpcode() != ISD::LOAD)
+  if ((!IsRoundOfExtLoad && FirstInput.getOpcode() != ISD::LOAD) ||
+      N->getNumOperands() == 1)
     return SDValue();
 
   for (int i = 1, e = N->getNumOperands(); i < e; ++i) {

Modified: llvm/trunk/test/CodeGen/PowerPC/crash.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/crash.ll?rev=342611&r1=342610&r2=342611&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/crash.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/crash.ll Wed Sep 19 20:09:15 2018
@@ -15,3 +15,20 @@ if.end:
   store i8 %bf.set, i8* %x3, align 4
   ret void
 }
+
+; A BUILD_VECTOR of 1 element caused a crash in combineBVOfConsecutiveLoads()
+; Test that this is no longer the case
+define signext i32 @test2() {
+entry:
+  %retval = alloca i32, align 4
+  %__a = alloca i128, align 16
+  %b = alloca i64, align 8
+  store i32 0, i32* %retval, align 4
+  %0 = load i128, i128* %__a, align 16
+  %splat.splatinsert = insertelement <1 x i128> undef, i128 %0, i32 0
+  %splat.splat = shufflevector <1 x i128> %splat.splatinsert, <1 x i128> undef, <1 x i32> zeroinitializer
+  %1 = bitcast <1 x i128> %splat.splat to <2 x i64>
+  %2 = extractelement <2 x i64> %1, i32 0
+  store i64 %2, i64* %b, align 8
+  ret i32 0
+}