[PATCH] D51494: Fix unwind information for floating point registers

[Oliver Stannard via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL342545: [ARM] Fix unwind information for floating point registers (authored by olista01, committed by ).

Changed prior to commit:
  https://reviews.llvm.org/D51494?vs=163550&id=166115#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D51494

Files:
  llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
  llvm/trunk/test/CodeGen/ARM/unwind-fp.ll


Index: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
===================================================================
--- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
+++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
@@ -1071,10 +1071,12 @@
   MCTargetStreamer &TS = *OutStreamer->getTargetStreamer();
   ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
   const MachineFunction &MF = *MI->getParent()->getParent();
-  const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
+  const TargetRegisterInfo *TargetRegInfo =
+    MF.getSubtarget().getRegisterInfo();
+  const MachineRegisterInfo &MachineRegInfo = MF.getRegInfo();
   const ARMFunctionInfo &AFI = *MF.getInfo<ARMFunctionInfo>();
 
-  unsigned FramePtr = RegInfo->getFrameRegister(MF);
+  unsigned FramePtr = TargetRegInfo->getFrameRegister(MF);
   unsigned Opc = MI->getOpcode();
   unsigned SrcReg, DstReg;
 
@@ -1131,7 +1133,9 @@
         if (MO.isUndef()) {
           assert(RegList.empty() &&
                  "Pad registers must come before restored ones");
-          Pad += 4;
+          unsigned Width =
+            TargetRegInfo->getRegSizeInBits(MO.getReg(), MachineRegInfo) / 8;
+          Pad += Width;
           continue;
         }
         RegList.push_back(MO.getReg());
Index: llvm/trunk/test/CodeGen/ARM/unwind-fp.ll
===================================================================
--- llvm/trunk/test/CodeGen/ARM/unwind-fp.ll
+++ llvm/trunk/test/CodeGen/ARM/unwind-fp.ll
@@ -0,0 +1,15 @@
+; RUN: llc < %s -mtriple=armv7a-arm-none-eabi | FileCheck %s
+
+target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
+target triple = "armv7-arm-none-eabi"
+
+define void @foo() minsize {
+entry:
+  ; CHECK: .vsave	{[[SAVE_REG:d[0-9]+]]}
+  ; CHECK-NEXT: .pad #8
+  ; CHECK-NEXT: vpush   {[[PAD_REG:d[0-9]+]], [[SAVE_REG]]}
+  ; CHECK: vpop     {[[PAD_REG]], [[SAVE_REG]]}
+  %a = alloca i32, align 4
+  call void asm sideeffect "", "r,~{d8}"(i32* %a)
+  ret void
+}


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