[llvm] r342545 - [ARM] Fix unwind information for floating point registers

[Oliver Stannard via llvm-commits]

Author: olista01
Date: Wed Sep 19 06:25:31 2018
New Revision: 342545

URL: http://llvm.org/viewvc/llvm-project?rev=342545&view=rev
Log:
[ARM] Fix unwind information for floating point registers

Fixes the unwind information generated for floating-point registers.
Previously, all padding registers were assumed to be four bytes wide. Now, the
width of the register is used to specify the amount of padding.

Patch by Jackson Woodruff!

Differential revision: https://reviews.llvm.org/D51494


Added:
    llvm/trunk/test/CodeGen/ARM/unwind-fp.ll
Modified:
    llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=342545&r1=342544&r2=342545&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Wed Sep 19 06:25:31 2018
@@ -1071,10 +1071,12 @@ void ARMAsmPrinter::EmitUnwindingInstruc
   MCTargetStreamer &TS = *OutStreamer->getTargetStreamer();
   ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
   const MachineFunction &MF = *MI->getParent()->getParent();
-  const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
+  const TargetRegisterInfo *TargetRegInfo =
+    MF.getSubtarget().getRegisterInfo();
+  const MachineRegisterInfo &MachineRegInfo = MF.getRegInfo();
   const ARMFunctionInfo &AFI = *MF.getInfo<ARMFunctionInfo>();
 
-  unsigned FramePtr = RegInfo->getFrameRegister(MF);
+  unsigned FramePtr = TargetRegInfo->getFrameRegister(MF);
   unsigned Opc = MI->getOpcode();
   unsigned SrcReg, DstReg;
 
@@ -1131,7 +1133,9 @@ void ARMAsmPrinter::EmitUnwindingInstruc
         if (MO.isUndef()) {
           assert(RegList.empty() &&
                  "Pad registers must come before restored ones");
-          Pad += 4;
+          unsigned Width =
+            TargetRegInfo->getRegSizeInBits(MO.getReg(), MachineRegInfo) / 8;
+          Pad += Width;
           continue;
         }
         RegList.push_back(MO.getReg());

Added: llvm/trunk/test/CodeGen/ARM/unwind-fp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/unwind-fp.ll?rev=342545&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/unwind-fp.ll (added)
+++ llvm/trunk/test/CodeGen/ARM/unwind-fp.ll Wed Sep 19 06:25:31 2018
@@ -0,0 +1,15 @@
+; RUN: llc < %s -mtriple=armv7a-arm-none-eabi | FileCheck %s
+
+target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
+target triple = "armv7-arm-none-eabi"
+
+define void @foo() minsize {
+entry:
+  ; CHECK: .vsave	{[[SAVE_REG:d[0-9]+]]}
+  ; CHECK-NEXT: .pad #8
+  ; CHECK-NEXT: vpush   {[[PAD_REG:d[0-9]+]], [[SAVE_REG]]}
+  ; CHECK: vpop     {[[PAD_REG]], [[SAVE_REG]]}
+  %a = alloca i32, align 4
+  call void asm sideeffect "", "r,~{d8}"(i32* %a)
+  ret void
+}