[PATCH] D52174: [TableGen][SubtargetEmitter] Add the ability for processor models to describe dependency breaking instructions.

[Clement Courbet via Phabricator via llvm-commits]

courbet added a comment.

Nice! I only have one comment on the schema, the rest is cosmetic.



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Comment at: include/llvm/Target/TargetInstrPredicate.td:292
+  // not exposed to the MC layer.
+  bit ExpandForMachineInstrOnly = machineInstrOnly;
+
----------------
This feels like a double negation to me. What about "ExpandForMC" ? It would also make it more future-rpoof if we want to expand to more stuff.


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Comment at: tools/llvm-mca/lib/InstrBuilder.cpp:458
+    if (IsDepBreaking) {
+      if ((Mask.isNullValue() && !RD.isImplicitRead()) ||
+          ((Mask.getBitWidth() > RD.UseIndex) && Mask[RD.UseIndex])) {
----------------
This could use two temporary bool variables for readability.


================
Comment at: utils/TableGen/CodeGenSchedule.cpp:257
+
+// Used by function `ProcessSTIPredicate` to construct a mask of machine
+// instruction operands.
----------------
*processSTIPredicate


https://reviews.llvm.org/D52174