[PATCH] D47882: [RISCV] Codegen for i8, i16, and i32 atomicrmw with RV32A

[Alex Bradbury via Phabricator via llvm-commits]

asb updated this revision to Diff 165968.
asb added a comment.

The patch has been updated so sign-extension is performed correct for part-word signed min/max operations.

All known issues are resolved. Final review would be very welcome.


https://reviews.llvm.org/D47882

Files:
  include/llvm/CodeGen/TargetLowering.h
  include/llvm/IR/Intrinsics.td
  include/llvm/IR/IntrinsicsRISCV.td
  lib/CodeGen/AtomicExpandPass.cpp
  lib/Target/RISCV/CMakeLists.txt
  lib/Target/RISCV/RISCV.h
  lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
  lib/Target/RISCV/RISCVISelLowering.cpp
  lib/Target/RISCV/RISCVISelLowering.h
  lib/Target/RISCV/RISCVInstrInfo.td
  lib/Target/RISCV/RISCVInstrInfoA.td
  lib/Target/RISCV/RISCVTargetMachine.cpp
  test/CodeGen/RISCV/atomic-rmw.ll

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