[llvm] r342441 - [PowerPC] Add Itineraries of IIC_IntMulHD for P7/P8

[QingShan Zhang via llvm-commits]

Author: qshanz
Date: Mon Sep 17 19:05:18 2018
New Revision: 342441

URL: http://llvm.org/viewvc/llvm-project?rev=342441&view=rev
Log:
[PowerPC] Add Itineraries of IIC_IntMulHD for P7/P8

When doing some instruction scheduling work, we noticed some missing itineraries.
Before we switch to machine scheduler, those missing itineraries might not have impact to actually scheduling, 
because we can still get same latency due to default values.

With machine scheduler, however, itineraries will have impact to scheduling.
eg: NumMicroOps will default to be 0 if there is NO itineraries for specific instruction class.
And most of the instruction class with itineraries will have NumMicroOps default to 1.

This will has impact on the count of RetiredMOps, affects the Pending/Available Queue, 
then causing different scheduling or suboptimal scheduling further.

Patch By: jsji (Jinsong Ji)
Differential Revision: https://reviews.llvm.org/D52040

Modified:
    llvm/trunk/lib/Target/PowerPC/PPCScheduleP7.td
    llvm/trunk/lib/Target/PowerPC/PPCScheduleP8.td
    llvm/trunk/test/CodeGen/PowerPC/mulld.ll

Modified: llvm/trunk/lib/Target/PowerPC/PPCScheduleP7.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCScheduleP7.td?rev=342441&r1=342440&r2=342441&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCScheduleP7.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCScheduleP7.td Mon Sep 17 19:05:18 2018
@@ -114,6 +114,10 @@ def P7Itineraries : ProcessorItineraries
                                                   P7_DU3, P7_DU4], 0>,
                                    InstrStage<1, [P7_FX1, P7_FX2]>],
                                   [4, 1, 1]>,
+  InstrItinData<IIC_IntMulHD    , [InstrStage<1, [P7_DU1, P7_DU2,
+                                                  P7_DU3, P7_DU4], 0>,
+                                   InstrStage<1, [P7_FX1, P7_FX2]>],
+                                  [4, 1, 1]>,
   InstrItinData<IIC_IntMulLI    , [InstrStage<1, [P7_DU1, P7_DU2,
                                                   P7_DU3, P7_DU4], 0>,
                                    InstrStage<1, [P7_FX1, P7_FX2]>],

Modified: llvm/trunk/lib/Target/PowerPC/PPCScheduleP8.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCScheduleP8.td?rev=342441&r1=342440&r2=342441&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCScheduleP8.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCScheduleP8.td Mon Sep 17 19:05:18 2018
@@ -90,6 +90,10 @@ def P8Itineraries : ProcessorItineraries
                                                   P8_DU4, P8_DU5, P8_DU6], 0>,
                                    InstrStage<1, [P8_FXU1, P8_FXU2]>],
                                   [4, 1, 1]>,
+  InstrItinData<IIC_IntMulHD    , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
+                                                  P8_DU4, P8_DU5, P8_DU6], 0>,
+                                   InstrStage<1, [P8_FXU1, P8_FXU2]>],
+                                  [4, 1, 1]>,
   InstrItinData<IIC_IntMulLI    , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3,
                                                   P8_DU4, P8_DU5, P8_DU6], 0>,
                                    InstrStage<1, [P8_FXU1, P8_FXU2]>],

Modified: llvm/trunk/test/CodeGen/PowerPC/mulld.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/mulld.ll?rev=342441&r1=342440&r2=342441&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/mulld.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/mulld.ll Mon Sep 17 19:05:18 2018
@@ -18,10 +18,10 @@ define void @bn_mul_comba8(i64* nocaptur
 
 ; CHECK-ITIN-LABEL: bn_mul_comba8:
 ; CHECK-ITIN:    mulhdu
-; CHECK-ITIN-NEXT:    mulhdu
 ; CHECK-ITIN-NEXT:    mulld
 ; CHECK-ITIN-NEXT:    mulhdu
 ; CHECK-ITIN-NEXT:    mulld
+; CHECK-ITIN-NEXT:    mulhdu
 
   %1 = load i64, i64* %a, align 8
   %conv = zext i64 %1 to i128