[PATCH] D52195: [DAGCombiner][x86] add transform/hook to decompose integer multiply into shift/add

[Sanjay Patel via Phabricator via llvm-commits]

spatel created this revision.
spatel added reviewers: RKSimon, craig.topper, efriedma, lebedev.ri.
Herald added a subscriber: mcrosier.

This is an alternative to https://reviews.llvm.org/D37896. I don't see a way to decompose multiplies generically without a target hook to tell us when it's profitable.

As a first step, I'm just trying to get the vector cases requested in PR34474:
https://bugs.llvm.org/show_bug.cgi?id=34474

The shakiest test diff here may be SSE4.1 code that uses 'pmulld' with a constant pool load. That can become 4 instructions like:

  movdqa %xmm0, %xmm1
  pslld $4, %xmm1
  paddd %xmm0, %xmm1
  movdqa %xmm1, %xmm0

...but I think despite the code-size increase, this is still better performing code. A scan of Agner's timing tables says pmulld is always at least 4 cycle latency, but possibly as much as 11 cycles. So replacing that with fast ops (and removing the constant load) should be a win even in the minimal case.


https://reviews.llvm.org/D52195

Files:
  include/llvm/CodeGen/TargetLowering.h
  lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  lib/Target/X86/X86ISelLowering.cpp
  lib/Target/X86/X86ISelLowering.h
  test/CodeGen/X86/rotate-extract-vector.ll
  test/CodeGen/X86/urem-seteq-vec-nonsplat.ll
  test/CodeGen/X86/urem-seteq-vec-splat.ll
  test/CodeGen/X86/vector-idiv-sdiv-128.ll
  test/CodeGen/X86/vector-idiv-sdiv-256.ll
  test/CodeGen/X86/vector-idiv-sdiv-512.ll
  test/CodeGen/X86/vector-idiv-udiv-128.ll
  test/CodeGen/X86/vector-idiv-udiv-256.ll
  test/CodeGen/X86/vector-idiv-udiv-512.ll
  test/CodeGen/X86/vector-mul.ll
  test/CodeGen/X86/vselect-avx.ll

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