[PATCH] D52052: [RegAllocGreedy] avoid using physreg candidates that cannot be correctly spilled

[Daniil Fukalov via Phabricator via llvm-commits]

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In https://reviews.llvm.org/D52052#1236976, @qcolombet wrote:

> My understanding is that you don't want split code to occur right before this instruction, but I would like to understand exactly what it is not allowed.


The amdgpu target has special exec mask register that specifies what lanes should execute current vector instruction. So a basic block created from "if/else" construction with vector condition may contain this exec mask register restore code in preamble.
E.g. instruction S_OR_SAVEEXEC_B64 at the start of a BB set (restores) exec mask register value to correctly execute "else" block. So a spilling code SplitKit tries to insert before such an instruction may be transformed into memory operation. And it can be incorrectly executed with a wrong exec mask.

> Indeed, it would be easy to trick your fix by building an artificial basic block just before that instruction, so it would be good to go back to the constraints and see how we can properly encode them.

Such new BB should take into account that "effective CFG" of vector operations depends on exec mask register value.


https://reviews.llvm.org/D52052