[PATCH] D52174: [TableGen][SubtargetEmitter] Add the ability for processor models to describe dependency breaking instructions.

[Matt Davis via Phabricator via llvm-commits]

mattd added a comment.

I like this change.  I have a few nits in the comments, but this looks good to me, caveat: I am not a tablegen expert.



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Comment at: include/llvm/Target/TargetInstrPredicate.td:245
+// Instances of this class can be used by processor scheduling models to
+// describe instruction that have a property in common.  For example,
+// InstructionEquivalenceClass definitions can be used to identify the set of
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*instructions


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Comment at: include/llvm/Target/TargetInstrPredicate.td:266
+// per each implicit and explicit input operand.  An empty set of broken
+// dependencies means: "explicit input register operands operands are
+// independent."
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*remove one of the  'operands' 


https://reviews.llvm.org/D52174