[PATCH] D52174: [TableGen][SubtargetEmitter] Add the ability for processor models to describe dependency breaking instructions.
Simon Pilgrim via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Sep 17 08:11:28 PDT 2018
RKSimon added inline comments.
================
Comment at: include/llvm/CodeGen/TargetSubtargetInfo.h:152
+ /// This function also sets bits in \param Mask related to input operands that
+ /// are not in a data dependency relatioship. There is one bit for each
+ /// machine operand; implicit operands follow explicit operands in the bit
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relationship
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Comment at: include/llvm/MC/MCInstrAnalysis.h:94
///
+ /// If \param Inst is a dependency breaking zero-idiom instruction for
+ /// processor \param CPUID, then bits of \param Mask which correspond to
----------------
\param MI
================
Comment at: include/llvm/MC/MCInstrAnalysis.h:114
+ /// input register operands are set. Other bits of the mask are cleared.
+ virtual bool isDependencyBreaking(const MCInst &MI, APInt &Mask,
+ unsigned CPUID) const {
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Please can you make it clear that Mask's bitwidth is total number of operands or just register operands?
https://reviews.llvm.org/D52174
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