[PATCH] D52171: [X86][SSE] Use ISD::MULHS for constant vXi16 ISD::SRA lowering (PR38151)

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon created this revision.
RKSimon added reviewers: craig.topper, spatel, lebedev.ri, andreadb.

Similar to the existing ISD::SRL constant vector shifts from https://reviews.llvm.org/D49562, this patch adds ISD::SRA support with ISD::MULHS.

As we're dealing with signed values, we have to handle shift by zero and shift by one special cases, so XOP+AVX2/AVX512 splitting/extension is still a better solution - really we should still use ISD::MULHS if one of the special cases are used but for now I've just left a TODO and filtered by isKnownNeverZero.


Repository:
  rL LLVM

https://reviews.llvm.org/D52171

Files:
  lib/Target/X86/X86ISelLowering.cpp
  test/CodeGen/X86/combine-sdiv.ll
  test/CodeGen/X86/vector-shift-ashr-128.ll
  test/CodeGen/X86/vector-shift-ashr-256.ll

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