[PATCH] D51932: [AMDGPU] Fix-up cases where writelane has 2 SGPR operands

Mon Sep 17 06:41:57 PDT 2018

arsenm added a comment.

I don't actually understand why this code is where it is? Why is SIFixSGPRCopies doing this? To clarify is this just an optimization? My initial reaction was that it was a fix, but looking at it again it seems like an optimization to me

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Comment at: lib/Target/AMDGPU/SIFixSGPRCopies.cpp:744-746
+            BuildMI(*MI.getParent(), MI, MI.getDebugLoc(),
+                    TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0)
+                .add(Src1);
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This should be a COPY?

Repository:
  rL LLVM

https://reviews.llvm.org/D51932