[PATCH] D52138: [Thumb] Add some integer abs testcases for different typesizes.
Ivan Kulagin via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Sat Sep 15 12:07:12 PDT 2018
ikulagin created this revision.
ikulagin added reviewers: t.p.northover, RKSimon, enderby, espindola.
Herald added a subscriber: llvm-commits.
ikulagin added inline comments.
================
Comment at: test/CodeGen/Thumb/iabs.ll:18
-; CHECK-NOT: 8:
}
----------------
Why do we need to check in such a manner without taking into account specific instructions but only counting their number?
Repository:
rL LLVM
https://reviews.llvm.org/D52138
Files:
test/CodeGen/Thumb/iabs.ll
Index: test/CodeGen/Thumb/iabs.ll
===================================================================
--- test/CodeGen/Thumb/iabs.ll
+++ test/CodeGen/Thumb/iabs.ll
@@ -1,5 +1,6 @@
; RUN: llc < %s -mtriple=thumb-unknown-unknown -filetype=obj -o %t.o
-; RUN: llvm-objdump -disassemble -arch-name=thumb %t.o | FileCheck %s
+; RUN: llvm-objdump -disassemble -arch-name=thumb %t.o | FileCheck --check-prefix=COUNT %s
+; RUN: llc < %s -mtriple=thumb-unknown-unknown | FileCheck %s
define i32 @test(i32 %a) {
%tmp1neg = sub i32 0, %a
@@ -9,12 +10,67 @@
; This test just checks that 4 instructions were emitted
-; CHECK: {{text}}
-; CHECK: 0:
-; CHECK-NEXT: 2:
-; CHECK-NEXT: 4:
-; CHECK-NEXT: 6:
+; COUNT-LABEL: {{text}}
+; COUNT: 0:
+; COUNT-NEXT: 2:
+; COUNT-NEXT: 4:
+; COUNT-NEXT: 6:
-; CHECK-NOT: 8:
+; COUNT-CHECK-NOT: 8:
}
+define i8 @test_i8(i8 %a) nounwind {
+; CHECK-LABEL: test_i8:
+; CHECK: %bb.0:
+; CHECK-NEXT: lsls r1, r0, #24
+; CHECK-NEXT: asrs r1, r1, #31
+; CHECK-NEXT: adds r0, r0, r1
+; CHECK-NEXT: eors r0, r1
+; CHECK-NEXT: bx lr
+ %tmp1neg = sub i8 0, %a
+ %b = icmp sgt i8 %a, -1
+ %abs = select i1 %b, i8 %a, i8 %tmp1neg
+ ret i8 %abs
+}
+
+define i16 @test_i16(i16 %a) nounwind {
+; CHECK-LABEL: test_i16:
+; CHECK: %bb.0:
+; CHECK-NEXT: lsls r1, r0, #16
+; CHECK-NEXT: asrs r1, r1, #31
+; CHECK-NEXT: adds r0, r0, r1
+; CHECK-NEXT: eors r0, r1
+; CHECK-NEXT: bx lr
+ %tmp1neg = sub i16 0, %a
+ %b = icmp sgt i16 %a, -1
+ %abs = select i1 %b, i16 %a, i16 %tmp1neg
+ ret i16 %abs
+}
+
+define i32 @test_i32(i32 %a) nounwind {
+; CHECK-LABEL: test_i32:
+; CHECK: %bb.0:
+; CHECK-NEXT: asrs r1, r0, #31
+; CHECK-NEXT: adds r0, r0, r1
+; CHECK-NEXT: eors r0, r1
+; CHECK-NEXT: bx lr
+ %tmp1neg = sub i32 0, %a
+ %b = icmp sgt i32 %a, -1
+ %abs = select i1 %b, i32 %a, i32 %tmp1neg
+ ret i32 %abs
+}
+
+define i64 @test_i64(i64 %a) nounwind {
+; CHECK-LABEL: test_i64:
+; CHECK: %bb.0:
+; CHECK-NEXT: asrs r2, r1, #31
+; CHECK-NEXT: adds r0, r0, r2
+; CHECK-NEXT: adcs r1, r2
+; CHECK-NEXT: eors r0, r2
+; CHECK-NEXT: eors r1, r2
+; CHECK-NEXT: bx lr
+ %tmp1neg = sub i64 0, %a
+ %b = icmp sgt i64 %a, -1
+ %abs = select i1 %b, i64 %a, i64 %tmp1neg
+ ret i64 %abs
+}
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