[PATCH] D52116: Introduce llvm.loop.parallel_accesses and llvm.access.group metadata.

Michael Kruse via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Fri Sep 14 12:06:29 PDT 2018


Meinersbur created this revision.
Meinersbur added reviewers: hfinkel, pekka, paul.redmond, reames, hsaito.
Herald added subscribers: dexonsmith, steven_wu, dmgreen, eraman, mehdi_amini.
Meinersbur added a dependent revision: D52117: Generate llvm.loop.parallel_accesses instead of llvm.mem.parallel_loop_access metadata..

The current llvm.mem.parallel_loop_access metadata has a problem in that it uses LoopIDs. LoopID unfortunately is not loop identifier. It is neither unique (there's even a regression test assigning the some LoopID to multiple loops; can otherwise happen if passes such as LoopVersioning make copies of entire loops) nor persistent (every time a property is removed/added from a LoopID's MDNode, it will also receive a new LoopID; this happens e.g. when calling Loop::setLoopAlreadyUnrolled()).
Since most loop transformation passes change the loop attributes (even if it just to mark that a loop should not be processed again as llvm.loop.isvectorized does, for the versioned and unversioned loop), the parallel access information is lost for any subsequent pass.

This patch unlinks LoopIDs and parallel accesses. llvm.mem.parallel_loop_access metadata on instruction is replaced by llvm.access.group metadata. llvm.access.group points to a single distinct MDNode with no operands (avoiding the problem to ever need to add/remove operands), called "access group". The LoopID then has an attribute  llvm.loop.parallel_accesses with all the access groups that are parallel (no dependencies carries by this loop).

This intentionally avoid any kind of "ID". Loops that are clones/have their attributes modifies retain the llvm.loop.parallel_accesses attribute. Access instructions that a cloned point to the same access group. It is not necessary for each access to have it's own "ID" MDNode, but those memory access instructions with the same behavior can be grouped together.

The behavior of llvm.mem.parallel_loop_access is not changed by this patch, but should be considered deprecated.

Possible extensions/follow-up patches:

- AutoUpgrade llvm.mem.parallel_loop_access to llvm.access.group such that we can remove its handling in the passes.
- Currently it is not possible to combine two access groups. This would require iterating through all of its uses of one access groups (MDNode's have no use lists, so we'd have to iterate over all instructions) and add the other one. We could allow access groups to reference other access groups, like:

    load ... !llvm.access.group !2
    load ... !llvm.access.group !3
  
  !0 = distinct !{!0, !{!"llvm.loop.parallel_accesses", !2}}
  !1 = distinct !{!1, !{!"llvm.loop.parallel_accesses", !3}}
  !2= distinct !{}
  !3= distinct !{}

introduce a new (non-distinct) access group that encompasses !2 and !3, e.g. when fusing into a new loop !4:

    load ... !llvm.access.group !2
    load ... !llvm.access.group !3
  
  !2= distinct !{}
  !3= distinct !{}
  !4 = distinct !{!1, !{!"llvm.loop.parallel_accesses", !5}}
  !5 = !{!2, !3}

This unfortunately requires walking an access group tree in LoopInfo::isAnnotatedParallel()


Repository:
  rL LLVM

https://reviews.llvm.org/D52116

Files:
  docs/LangRef.rst
  include/llvm/IR/LLVMContext.h
  include/llvm/Transforms/Utils/LoopUtils.h
  lib/Analysis/LoopInfo.cpp
  lib/IR/LLVMContext.cpp
  lib/Transforms/InstCombine/InstCombineCalls.cpp
  lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp
  lib/Transforms/Scalar/LoopVersioningLICM.cpp
  lib/Transforms/Scalar/SROA.cpp
  lib/Transforms/Scalar/Scalarizer.cpp
  lib/Transforms/Utils/InlineFunction.cpp
  lib/Transforms/Utils/Local.cpp
  lib/Transforms/Utils/LoopUtils.cpp
  lib/Transforms/Utils/SimplifyCFG.cpp
  test/ThinLTO/X86/lazyload_metadata.ll
  test/Transforms/Inline/parallel-loop-md.ll
  test/Transforms/InstCombine/loadstore-metadata.ll
  test/Transforms/InstCombine/mem-par-metadata-memcpy.ll
  test/Transforms/LoopVectorize/X86/force-ifcvt.ll
  test/Transforms/LoopVectorize/X86/illegal-parallel-loop-uniform-write.ll
  test/Transforms/LoopVectorize/X86/parallel-loops-after-reg2mem.ll
  test/Transforms/LoopVectorize/X86/parallel-loops.ll
  test/Transforms/LoopVectorize/X86/pr34438.ll
  test/Transforms/LoopVectorize/X86/vect.omp.force.ll
  test/Transforms/LoopVectorize/X86/vect.omp.force.small-tc.ll
  test/Transforms/LoopVectorize/X86/vector_max_bandwidth.ll
  test/Transforms/SROA/mem-par-metadata-sroa.ll
  test/Transforms/Scalarizer/basic.ll
  test/Transforms/SimplifyCFG/combine-parallel-mem-md.ll

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