[PATCH] D52082: [Arm][AsmParser] Restrict register list size for VSTM/VLDM

[Luke Cheeseman via Phabricator via llvm-commits]

LukeCheeseman created this revision.
Herald added a reviewer: javed.absar.
Herald added subscribers: llvm-commits, kristof.beyls.
LukeCheeseman retitled this revision from "[AArch64][AsmParser] Restrict register list size for VSTM/VLDM" to "[Arm][AsmParser] Restrict register list size for VSTM/VLDM".
Herald added a subscriber: chrib.

- The assembler accepts VSTM/VLDM with register lists (specifically double registers lists) with more than 16 registers specified
- The Arm architecture reference manual says this instruction must not contain more than 16 registers when the registers are doubleword registers


Repository:
  rL LLVM

https://reviews.llvm.org/D52082

Files:
  lib/Target/ARM/AsmParser/ARMAsmParser.cpp
  test/MC/ARM/single-precision-fp.s


Index: test/MC/ARM/single-precision-fp.s
===================================================================
--- test/MC/ARM/single-precision-fp.s
+++ test/MC/ARM/single-precision-fp.s
@@ -171,6 +171,19 @@
 @ CHECK-ERRORS: error: instruction requires: double precision VFP
 @ CHECK-ERRORS-NEXT: vrintm.f64 d3, d2
 
+        vstm r4, {d15-d30}
+        vstm r4, {d15-d31}
+        vstm r4, {s15-s31}
+        vldm r4, {d15-d30}
+        vldm r4, {d15-d31}
+        vldm r4, {s15-s31}
+@ CHECK:  vstmia  r4, {d15, d16, d17, d18, d19, d20, d21, d22, d23, d24, d25, d26, d27, d28, d29, d30}
+@ CHECK-ERRORS: error: list of registers must be at least 1 and at most 16
+@ CHECK:  vstmia  r4, {s15, s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31}
+@ CHECK:  vldmia  r4, {d15, d16, d17, d18, d19, d20, d21, d22, d23, d24, d25, d26, d27, d28, d29, d30}
+@ CHECK-ERRORS: error: list of registers must be at least 1 and at most 16
+@ CHECK:  vldmia  r4, {s15, s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31}
+
         @ Double precisionish operations that actually *are* allowed.
         vldr d0, [sp]
         vstr d3, [sp]
Index: lib/Target/ARM/AsmParser/ARMAsmParser.cpp
===================================================================
--- lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -6839,6 +6839,15 @@
                    "destination operands must be sequential");
     break;
   }
+  case ARM::VLDMDIA:
+  case ARM::VSTMDIA: {
+    ARMOperand &Op = static_cast<ARMOperand&>(*Operands[3]);
+    auto &RegList = Op.getRegList();
+    if (RegList.size() < 1 || RegList.size() > 16)
+      return Error(Operands[3]->getStartLoc(),
+                   "list of registers must be at least 1 and at most 16");
+    break;
+  }
   }
 
   return false;


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