[PATCH] D18086: Fix default processor name for armv6k.

[Peter Smith via Phabricator via llvm-commits]

peter.smith added a comment.

There isn't a processor called ARM1176J-S, only ARM1176JZ-S and ARM1176JZF-S. I've already left a comment about J and S. Z is for Trustzone and F is for hardware floating point. There isn't a good external source for all the possible arm 11 CPU names unfortunately. There is a page of trademarks that contains all the ones that I know about https://www.arm.com/company/policies/trademarks/arm-trademark-list/arm11-trademark.



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Comment at: include/llvm/Support/ARMTargetParser.def:182
 ARM_CPU_NAME("arm1136jz-s", AK_ARMV6, FK_NONE, false, AEK_NONE)
-ARM_CPU_NAME("arm1176j-s", AK_ARMV6K, FK_NONE, true, AEK_NONE)
+ARM_CPU_NAME("arm1176jz-s", AK_ARMV6K, FK_NONE, false, AEK_NONE)
+ARM_CPU_NAME("arm1176jzf-s", AK_ARMV6K, FK_VFPV2, true, AEK_NONE)
----------------
rengolin wrote:
> srhines wrote:
> > This uses the same name as line 184, which seems like a bug to me.
> I think that's what @labrinea was talking about.
> 
> Can anyone from Arm confirm what "j-s" really is, if it is anything at all?
> 
> I had so many conversations about this in the past and all of them got me even more confused than before.
The j stands for Jazelle (https://en.wikipedia.org/wiki/Jazelle) which was a Thumb like mode that could be entered with I think the BXJ mode. This would allow the processor to execute a handful of the most common Java bytecodes. The only affect that this would have on LLVM would potentially be to enable the BXJ instruction. Personally I don't think it is worth it given that direct execution of bytecodes lost out to JIT compilers so I don't expect anyone actually wanting to use it.

The s stands for synthesizable. This means that the design was available to hardware licensees in VHDL rather than as a fixed macrocell. Obviously this makes no difference to code-generation.




https://reviews.llvm.org/D18086