[PATCH] D52072: [PowerPC] Fix the assert of combineBVOfConsecutiveLoads when element num is 1
Zixuan Wu via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Sep 13 21:58:34 PDT 2018
wuzish created this revision.
wuzish added reviewers: hfinkel, nemanjai.
Herald added subscribers: kbarton, hiraditya.
Building a vector out of multiple loads can be converted to a load of the vector type if the loads are consecutive. But the special condition is that the element number is 1, such as <1 x i128>. So just early exit to fix the assert.
Repository:
rL LLVM
https://reviews.llvm.org/D52072
Files:
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/test/CodeGen/PowerPC/crash.ll
Index: llvm/test/CodeGen/PowerPC/crash.ll
===================================================================
--- llvm/test/CodeGen/PowerPC/crash.ll
+++ llvm/test/CodeGen/PowerPC/crash.ll
@@ -15,3 +15,18 @@
store i8 %bf.set, i8* %x3, align 4
ret void
}
+
+define signext i32 @test2() {
+entry:
+ %retval = alloca i32, align 4
+ %__a = alloca i128, align 16
+ %b = alloca i64, align 8
+ store i32 0, i32* %retval, align 4
+ %0 = load i128, i128* %__a, align 16
+ %splat.splatinsert = insertelement <1 x i128> undef, i128 %0, i32 0
+ %splat.splat = shufflevector <1 x i128> %splat.splatinsert, <1 x i128> undef, <1 x i32> zeroinitializer
+ %1 = bitcast <1 x i128> %splat.splat to <2 x i64>
+ %2 = extractelement <2 x i64> %1, i32 0
+ store i64 %2, i64* %b, align 8
+ ret i32 0
+}
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
===================================================================
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -11890,7 +11890,8 @@
IsRoundOfExtLoad = LD->getExtensionType() == ISD::EXTLOAD;
}
// Not a build vector of (possibly fp_rounded) loads.
- if (!IsRoundOfExtLoad && FirstInput.getOpcode() != ISD::LOAD)
+ if ((!IsRoundOfExtLoad && FirstInput.getOpcode() != ISD::LOAD) ||
+ N->getNumOperands() == 1)
return SDValue();
for (int i = 1, e = N->getNumOperands(); i < e; ++i) {
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