[PATCH] D51873: [AArch64] Add support for the ABS dag node and testcases for integer abs.

[Ivan Kulagin via Phabricator via llvm-commits]

ikulagin updated this revision to Diff 165384.
ikulagin added a comment.

> Please rebase after https://reviews.llvm.org/rL342156

Rebase


Repository:
  rL LLVM

https://reviews.llvm.org/D51873

Files:
  lib/Target/AArch64/AArch64ISelLowering.cpp
  test/CodeGen/AArch64/iabs.ll


Index: test/CodeGen/AArch64/iabs.ll
===================================================================
--- test/CodeGen/AArch64/iabs.ll
+++ test/CodeGen/AArch64/iabs.ll
@@ -3,9 +3,9 @@
 define i8 @test_i8(i8 %a) nounwind {
 ; CHECK-LABEL: test_i8:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:  sbfx w8, w0, #7, #1
-; CHECK-NEXT:  add w9, w0, w8
-; CHECK-NEXT:  eor w0, w9, w8
+; CHECK-NEXT:  sxtb w8, w0
+; CHECK-NEXT:  cmp w8, #0
+; CHECK-NEXT:  cneg w0, w8, mi
 ; CHECK-NEXT:  ret
   %tmp1neg = sub i8 0, %a
   %b = icmp sgt i8 %a, -1
@@ -16,9 +16,9 @@
 define i16 @test_i16(i16 %a) nounwind {
 ; CHECK-LABEL: test_i16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:  sbfx w8, w0, #15, #1
-; CHECK-NEXT:  add w9, w0, w8
-; CHECK-NEXT:  eor w0, w9, w8
+; CHECK-NEXT:  sxth w8, w0
+; CHECK-NEXT:  cmp w8, #0
+; CHECK-NEXT:  cneg w0, w8, mi
 ; CHECK-NEXT:  ret
   %tmp1neg = sub i16 0, %a
   %b = icmp sgt i16 %a, -1
@@ -41,8 +41,9 @@
 define i64 @test_i64(i64 %a) nounwind {
 ; CHECK-LABEL: test_i64:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:  cmp x0, #0
-; CHECK-NEXT:  cneg x0, x0, mi
+; CHECK-NEXT:  fmov d0, x0
+; CHECK-NEXT:  abs d0, d0
+; CHECK-NEXT:  fmov x0, d0
 ; CHECK-NEXT:  ret
   %tmp1neg = sub i64 0, %a
   %b = icmp sgt i64 %a, -1
Index: lib/Target/AArch64/AArch64ISelLowering.cpp
===================================================================
--- lib/Target/AArch64/AArch64ISelLowering.cpp
+++ lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -156,6 +156,10 @@
     addQRTypeForNEON(MVT::v4i32);
     addQRTypeForNEON(MVT::v2i64);
     addQRTypeForNEON(MVT::v8f16);
+
+    // The AArch64 SIMD extension supports the scalar variant
+    // of the ABS instruction.
+    setOperationAction(ISD::ABS, MVT::i64, Legal);
   }
 
   // Compute derived properties from the register classes


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