[PATCH] D52052: [RegAllocGreedy] avoid using physreg candidates that cannot be correctly spilled

[Daniil Fukalov via Phabricator via llvm-commits]

dfukalov created this revision.
dfukalov added reviewers: rampitec, MatzeB.
dfukalov added a project: AMDGPU.
Herald added subscribers: tpr, nhaehnle, jvesely, qcolombet.

For the AMDGPU target if a MBB contains exec mask restore preamble, SplitEditor may get state when it cannot insert a spill instruction.

E.g. for a MIR

  bb.100:
      %1 = S_OR_SAVEEXEC_B64 %2, implicit-def $exec, implicit-def $scc, implicit $exec

and if the regalloc will try to allocate a virtreg to the physreg already assigned to virtreg %1, it should insert spill instruction //before// the S_OR_SAVEEXEC_B64 instruction.
But it is not possible since can generate incorrect code in terms of exec mask.

The change makes regalloc to ignore such physreg candidates.


Repository:
  rL LLVM

https://reviews.llvm.org/D52052

Files:
  lib/CodeGen/RegAllocGreedy.cpp
  lib/CodeGen/SplitKit.h
  test/CodeGen/AMDGPU/spill-before-exec.mir

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