[PATCH] D51502: [X86] Fix register resizings for inline assembly register operands.

[Nick Desaulniers via Phabricator via llvm-commits]

nickdesaulniers accepted this revision.
nickdesaulniers added a comment.
This revision is now accepted and ready to land.

There we go, clang now even produces one less relocation than gcc, but otherwise the same instructions, from my test case:

  00000000 <foo>:
     0:   e8 0b 00 00 00          call   10 <bar>
     5:   89 d0                   mov    %edx,%eax
     7:   89 ca                   mov    %ecx,%edx
     9:   c3                      ret

The disassembly of individual translation units from the Linux kernel also looks correct, though clang has other issues compiling a working 32b x86 Linux kernel, so I can't test this completely.  But based on the smaller cases, this code looks correct.

Thanks Nirav!



================
Comment at: llvm/test/CodeGen/X86/physreg-pairs.ll:4
+
+; To match GCCs behavior in assigning 64-bit values ot a 32-bit
+; register we bind to the value to the pair (the given register, the following
----------------
`GCC's`
`values to`


================
Comment at: llvm/test/CodeGen/X86/physreg-pairs.ll:6
+; register we bind to the value to the pair (the given register, the following
+; register) in the sequence.  EAX, EDX, ECX, EBX, ESI, EDI, EBP, ESP. There
+; is no wrapping, so this will fail given ESP.
----------------
I find this sentence slightly hard to follow.  Would you mind rewording it to something along the lines of:

> To match GCC's behavior in assigning 64-bit values to a 32-bit
> register, we bind the pair (the given register, the following
> register) from the sequence
> EAX, EDX, ECX, EBX, ESI, EDI, EBP, ESP,
> to the value.  There is no wrapping from the sequence, so this
> will fail given ESP.


Repository:
  rL LLVM

https://reviews.llvm.org/D51502