[PATCH] D51815: [RISCV] Fix decoding of invalid instruction with C extension enabled.

[Ana Pazos via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL342159: [RISCV] Fix decoding of invalid instruction with C extension enabled. (authored by apazos, committed by ).
Herald added subscribers: llvm-commits, jrtc27.

Changed prior to commit:
  https://reviews.llvm.org/D51815?vs=164524&id=165337#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D51815

Files:
  llvm/trunk/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
  llvm/trunk/lib/Target/RISCV/RISCVInstrInfoC.td
  llvm/trunk/test/MC/Disassembler/RISCV/invalid-instruction.txt


Index: llvm/trunk/test/MC/Disassembler/RISCV/invalid-instruction.txt
===================================================================
--- llvm/trunk/test/MC/Disassembler/RISCV/invalid-instruction.txt
+++ llvm/trunk/test/MC/Disassembler/RISCV/invalid-instruction.txt
@@ -0,0 +1,13 @@
+# RUN: not llvm-mc -disassemble -triple=riscv32 -mattr=+c < %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -disassemble -triple=riscv64 -mattr=+c < %s 2>&1 | FileCheck %s
+#
+# Test generated by a LLVM MC Disassembler Protocol Buffer Fuzzer
+# for the RISC-V assembly language.
+
+# This should not decode as c.addi4spn with 0 imm when compression is enabled.
+[0x00 0x00]
+# CHECK: warning: invalid instruction encoding
+
+# This should not decode as c.addi16sp with 0 imm when compression is enabled.
+[0x01 0x61]
+# CHECK: warning: invalid instruction encoding
Index: llvm/trunk/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
===================================================================
--- llvm/trunk/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ llvm/trunk/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -212,6 +212,15 @@
 }
 
 template <unsigned N>
+static DecodeStatus decodeUImmNonZeroOperand(MCInst &Inst, uint64_t Imm,
+                                             int64_t Address,
+                                             const void *Decoder) {
+  if (Imm == 0)
+    return MCDisassembler::Fail;
+  return decodeUImmOperand<N>(Inst, Imm, Address, Decoder);
+}
+
+template <unsigned N>
 static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm,
                                       int64_t Address, const void *Decoder) {
   assert(isUInt<N>(Imm) && "Invalid immediate");
@@ -222,6 +231,15 @@
 }
 
 template <unsigned N>
+static DecodeStatus decodeSImmNonZeroOperand(MCInst &Inst, uint64_t Imm,
+                                             int64_t Address,
+                                             const void *Decoder) {
+  if (Imm == 0)
+    return MCDisassembler::Fail;
+  return decodeSImmOperand<N>(Inst, Imm, Address, Decoder);
+}
+
+template <unsigned N>
 static DecodeStatus decodeSImmOperandAndLsl1(MCInst &Inst, uint64_t Imm,
                                              int64_t Address,
                                              const void *Decoder) {
Index: llvm/trunk/lib/Target/RISCV/RISCVInstrInfoC.td
===================================================================
--- llvm/trunk/lib/Target/RISCV/RISCVInstrInfoC.td
+++ llvm/trunk/lib/Target/RISCV/RISCVInstrInfoC.td
@@ -167,7 +167,7 @@
                           [{return isShiftedUInt<8, 2>(Imm) && (Imm != 0);}]> {
   let ParserMatchClass = UImmAsmOperand<10, "Lsb00NonZero">;
   let EncoderMethod = "getImmOpValue";
-  let DecoderMethod = "decodeUImmOperand<10>";
+  let DecoderMethod = "decodeUImmNonZeroOperand<10>";
   let MCOperandPredicate = [{
     int64_t Imm;
     if (!MCOp.evaluateAsConstantImm(Imm))
@@ -182,7 +182,7 @@
                             [{return (Imm != 0) && isShiftedInt<6, 4>(Imm);}]> {
   let ParserMatchClass = SImmAsmOperand<10, "Lsb0000NonZero">;
   let EncoderMethod = "getImmOpValue";
-  let DecoderMethod = "decodeSImmOperand<10>";
+  let DecoderMethod = "decodeSImmNonZeroOperand<10>";
   let MCOperandPredicate = [{
     int64_t Imm;
     if (!MCOp.evaluateAsConstantImm(Imm))


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