[PATCH] D51932: [AMDGPU] Fix-up cases where writelane has 2 SGPR operands

[David Stuttard via Phabricator via llvm-commits]

dstuttard updated this revision to Diff 165274.
dstuttard added a comment.

Moved foldToImm into SIInstrInfo as suggested
Implemented check in verifyInstruction and checked that it worked when the fix was removed


Repository:
  rL LLVM

https://reviews.llvm.org/D51932

Files:
  lib/Target/AMDGPU/SIFixSGPRCopies.cpp
  lib/Target/AMDGPU/SIInstrInfo.cpp
  lib/Target/AMDGPU/SIInstrInfo.h
  lib/Target/AMDGPU/SIPeepholeSDWA.cpp
  test/CodeGen/AMDGPU/llvm.amdgcn.writelane.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D51932.165274.patch
Type: text/x-patch
Size: 9928 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20180913/40383be8/attachment.bin>